Intel® Stratix® 10 SoC FPGA Boot User Guide

ID 683847
Date 1/20/2023
Document Table of Contents

3.2.3. Single SDM Flash

In this case, the Quad SPI flash connected to the SDM contains all the data required for configuring and booting the system, including the configuration bitstream, bootloader and OS files.

Note: When you use the HPS to access the SDM Quad SPI, it operates at a lower bandwidth of ~4-6 MB/s. This is due to the high latency of the PSI link between HPS and SDM, and the fact that all transfers are done in Programmed IO (PIO) mode, instead of DMA mode.

Software running on the HPS must request permission from the SDM to get exclusive access to the QSPI before using it. This is already implemented in the U-Boot and UEFI bootloaders supported by Intel® .

Depending on the boot stage that performs the FPGA configuration, you have the following options for storing the FPGA core and I/O configuration file:
  • An SDM flash storage partition—In this case the SSBL initiates configuration
  • In the OS file system—In this case the OS initiates configuration
Figure 9. HPS Boot First Layout with Quad SPI

Did you find the information on this page useful?

Characters remaining:

Feedback Message