Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 1/14/2022
Public
Document Table of Contents

1. Terms and Acronyms

Updated for:
Intel® Quartus® Prime Design Suite 21.4
Table 1.  Acronyms
Term Definition
PCIe* Peripheral Component Interconnect Express ( PCI Express* )
DMA Direct Memory Access
MCDMA Multi Channel Direct Memory Access
PIO Programmed Input/Output
H2D Host-to-Device
D2H Device-to-Host
H2DDM Host-to-Device Data Mover
D2HDM Device-to-Host Data Mover
QCSR Queue Control and Status register
GCSR General Control and Status Register
IP Intellectual Property
HIP Hard IP
PD Packet Descriptor
QID Queue Identification
TIDX Queue Tail Index (pointer)
HIDX Queue Head Index (pointer)
TLP Transaction Layer Packet
IMMWR Immediate Write Operation
MRRS Maximum Read Request Size
CvP Configuration via Protocol
PBA Pending Bit Array
API Application Programming Interface
Avalon® -MM (or AVMM) Avalon® Memory-Mapped Interface
Avalon® -ST (or AVST) Avalon® Streaming Interface
SOF Start of a File (or packet) for streaming
EOF End of a File (or packet) for streaming
File (or Packet) A group of descriptors defined by SOF and EOF bits of the descriptor for the streaming. At Avalon-ST user interface, a file (or packet) is marked by means of sof/eof.
BAM Bursting Avalon-MM Master
BAS Bursting Avalon-MM Slave
MSI Message Signaled Interrupt
MSI-X Message Signaled Interrupt - Extended
FLR Functional Level Reset
FAE Field Applications Engineer
DPDK Data Path Development Kit
SR-IOV Single Root I/O Virtualization
PMD Poll Mode Driver