Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 1/14/2022
Public

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3.1.9. Control Registers

The Multi Channel DMA IP for PCI Express provides 4 MB of control register space that is internally mapped to PCIe BAR0. The control register block contains the all the required registers to support the DMA operations. This includes QCSR space for individual queue control, MSI-X for interrupt generations, and GCSR for general global information.

The following table shows 4MB space mapped for each function in PCIe config space through BAR0.
Table 20.  Control Registers
Address Space Range Size Description
QCSR (D2H, H2D) 22’h00_0000 - 22’h0F_FFFF 1 MB Individual queue control and status registers, up to 2048 D2H and 2048 H2D queues
MSI-X (Table and PBA) 22’h10_0000 - 22’h1F_FFFF 1 MB MSI-X Table and PBA space
GCSR 22’h20_0000 - 22’h2F_FFFF 1 MB General DMA control and status registers. Only for PF0.
Reserved 22’h30_0000 – 22’h3F_FFFF 1­MB Reserved
Note: For more information on Control registers, refer to Control Register (GCSR)

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