Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 1/14/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.4. Config Slave

This interface is applicable only in Root Port mode. The Config Slave (CS) is an AVMM non-bursting interface and essentially converts single-cycle, Avalon-MM read and write transactions into AVST reads and writes for the PCIe configuration TLPs to be sent to PCIe Hard IP (to be sent over the PCIe link). This module also processes the completion TLPs (Cpl and CplD) it receives in return.

CS module converts the AVMM request into a configuration TLP with a fixed TAG value (decimal 255) assigned to it and sends it to scheduler. One unique TAG is enough as it doesn’t support more than one outstanding transaction. This unique TAG helps in rerouting the completions to CS module.

Re-routing the completion is handled at the top level and since only 1 NP outstanding is needed, the TLP RX scheduler parses the completion field to decode the completion on a fixed TAG and route the transaction over to CS.

Figure 10. Avalon-MM Config Slave Module

Config Slave AVMM Address

Config Slave interface supports 29-bit format in Intel® Quartus® Prime Pro Edition v21.1 and Intel® Quartus® Prime Pro Edition v21.2 and 14-bit format in Intel® Quartus® Prime Pro Edition v21.3 and onward.

Figure 11. 29 bit Address Format
Figure 12. 14 bit Address Format

CS AVMM address is limited to 14 bits as shown below and the 2 MSB bits [13:12] differentiates whether [11:0] content of Address is used to form a Cfg TLP or used to write to/read from CS local registers.

Table 21.  
CS Local Address Offset Name Access Comment
0x0000 Scratch Pad Register RW
0x0004 BDF Register RW {Bus [7:0], Device [4:0], Function [2:0]}
0x0008 Error Register RW1C
Table 22.  Configuration Access Mechanism in 29-bit and 14-bit addressing
Access 29-bit Address 14-bit Address
EP Config Space Write Single Write: AVMM write to EP Register address (AVMM address includes BDF+ Register) with actual data Two Writes:
  • Write BDF info to 0x0004 (with 13th bit set to 1)
  • AVMM Write to EP Register address (with 13th bit set to 0) with actual data
EP Config Space Read
  • AVMM read to EP Register address (AVMM address includes BDF+Register)
  • Type1/Type0 based on 28th bit
  • CplD data is available on AVMM read data bus
  • One AVMM write of BDF info to 0x0004 (with 13th bit set to 1)
  • One AVMM read to EP Register address (with 13th bit set to 0)
  • Type1/Type0 based on 12th bit
  • CplD data is available on AVMM read data bus

Did you find the information on this page useful?

Characters remaining:

Feedback Message