Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 1/14/2022
Public

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8.2.5. Software Flow

Figure 39. DPDK Poll-Mode Driver Software Flow

Step 1

  • Based on the specified number of queues, application sets up Tx and Rx queues.
  • MCDMA Poll mode driver (PMD) takes care of memory management and reserves a portion of physical memory with specified alignment and boundary.
  • PMD initializes following registers in QCSR associated with the queue, which includes Starting address of descriptors, queue size, write back address for Consumed Head, payload size in D2H descriptors and then enables the channels.
  • QCSR registers:
    • Q_START_ADDR_L (Offset 8’h08)
    • Q_START_ADDR_H (Offset 8’h0C)
    • Q_SIZE (Offset 8’h10)
    • Q_CONSUMED_HEAD_ADDR_L (Offset 8’h20)
    • Q_CONSUMED_HEAD_ADDR_H (Offset 8’h24)
    • Q_BATCH_DELAY (Offset 8’h28)
    • Q_CTRL (Offset 8’h00)
    • QDMA_REGS_2_Q_DEBUG_STATUS_4 (Q_PYLD_COUNT) (Offset 8'h44)
  • Once all the queues are configured it then starts the device.
  • Q Application creates the thread based on the number of queues specified.

Step 2

Thread requests for new descriptor to submit the request and updates the required field i.e., descriptor index, SOF, EOF, Payload, MSI-X enable and writeback enable.

Step 3

After initializing descriptor ring buffer, the McDMA PMD writes number of descriptor updates into tail register of QCSR region. On every descriptor update the tail pointer is increased by 1. QCSR tail pointer register: Q_TAIL_POINTER (Offset 8’h14)

Step 4

  • Once the tail pointer write happens, MCDMA IP fetches descriptors from host memory starting from the programmed Q_START_ADDR_L/H address.
  • MCDMA IP parses the descriptor content to find the sources, destination addresses and length of the data from descriptor and starts DMA operation.

Step 5

Once descriptor processing is completed, IP notifies the completion status based on following methods, which can be enabled in each descriptor.
  • Either based on MSI-X Interrupt: MCDMA IP sends MSI-X interrupt to host if enabled in Q_CTRL.
  • Writeback: MCDMA IP updates Q_CONSUMED_HEAD_ADDR_L/H, if writeback is enabled in Q_CTRL.

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