Multi Channel DMA Intel® FPGA IP for PCI Express User Guide
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4.5. Bursting Avalon-MM Master (BAM) Interface
Signal Name | I/O Type | Description |
---|---|---|
bam_address_o[<n>:0] | Output | Represents a byte address. The value of address must align to the data width. <n>: {vfactive+$clog2(PF_NUM)+11+3+BAR_addr_width}-1, where vfactive=1, PF_NUM=number of PFs enabled, 11=$clog2(2048), 3=bar_num width, BAR_addr_width= 22 bits (H-Tile) / max(BAR_addr_width) (P-Tile and F-Tile) |
x16: bam_byteenable_o[63:0] x8: bam_byteenable_o[31:0] |
Output | Enables one or more specific byte lanes during transfers on interfaces |
x16: bam_burstcount_o[3:0] x8: bam_burstcount_o[4:0] |
Output | Used by a bursting master to indicate the number of transfers in each burst. |
bam_read_o | Output | Asserted to indicate a read transfer. |
x16: bam_readdata_i[511:0] x8: bam_readdata_i[255:0] |
Input | Read data from the user logic in response to a read transfer |
bam_readdatavalid_i | Input | When asserted, indicates that the readdata signal contains valid data. For a read burst with burstcount value <n>, the readdatavalid signal must be asserted <n> times, once for each readdata item. |
bam_write_o | Output | Asserted to indicate a write transfer |
x16: bam_writedata_o[511:0] x8: bam_writedata_o[255:0] |
Output | Data for write transfers |
bam_waitrequest_i | Input | When asserted, indicates that the Avalon-MM slave is not ready to respond to a request. |