Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 1/14/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

12. Revision History for Multi Channel DMA Intel FPGA IP for PCI Express User Guide

Date Intel® Quartus® Prime Version IP Version Changes
2022.01.14 21.4

21.3.0 [H-Tile]

2.2.0 [P-Tile]

1.1.0 [F-Tile]

2021.10.29 21.3

21.2.0 [H-Tile]

2.1.0 [P-Tile]

1.0.0 [F-Tile]

  • Recommended Speed Grades table updated with F-Tile support information
  • Resource Utilization tables updated
  • Release Information updated
  • Valid user modes and required functional blocks table updated
  • Address format information added to Config Slave
  • Multi Channel DMA IP for PCI Express Port List (P-Tile and F-Tile) figure updated with F-Tile information
  • Config TL Interface signal table updated
  • F-Tile support information added to Configuration Intercept Interface (EP Only)
  • F-Tile support information added to Parameters (P-Tile and F-Tile) Chapter
  • MCDMA IP Software Driver Differentiation table added
  • Network Device Driver information added in Multi Channel DMA IP Kernel Mode Network Device Driver
  • Debug Toolkit information added
2021.08.16 21.2

21.1.0 [H-Tile]

2.0.0 [P-Tile]

  • Fixed H-Tile IP revision number
  • Added 500 MHz support for P-Tile MCDMA IP
  • Added P-Tile single port Avalon-ST DMA up to 256 channels
  • Added MCDMA IP DPDK Poll-Mode based Driver
  • Added MCDMA IP Kernel Mode (No SRIOV) Driver
2021.05.28 21.1

2.0.0 [H-Tile]

1.0.0 [P-Tile]

  • PCIe Gen4 (P-Tile) Support
  • Support for x8 link width
  • MCDMA 1 port AVST interface
  • SR-IOV support
  • Root Port support (IP only)
  • Config Slave interface for RP
2020.07.20 20.2

20.0.0 (H-Tile)

Initial Release