Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 1/14/2022

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Document Table of Contents

3.8.3. Application Specific Bits

Table 30.  Application Specific Bits
Bit [2] Bit [1] Bit [0] Description
0 1 1


0 1 0


0 0 1

Data mover considers this as MSI/MSI-X/WB and picks the address/data from AVST sink interface in D2H direction (d2hdm_desc).

Not applicable for H2D, and external DMA controller must drive 0.

0 0 0

No interrupt from external DMA controller and expecting the external DMA to use the descriptor format to request sending MSI-X with MSI-X vector number (MSI-X_Vector_num).

Not applicable in D2H direction.

In current release of the support for external DMA controller, the DMA controller has the descriptor stored internally to figure out generation of an interrupt. The DMA controller generates the interrupt by queueing an MSI-X/MSI write to the D2H Data Mover’s descriptor queue with MM_mode=0 and application specific bits.