Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 1/14/2022
Public

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9. Registers

The Multi Channel DMA IP for PCI Express provides configuration, control and status registers to support the DMA operations including:
  • D2H and H2D Queue control and status (QCSR)
  • MSI-X Table and PBA for interrupt generation
  • General/global DMA control (GCSR)
These Multi Channel DMA registers are mapped to BAR0 of a function.
Note: GCSR is only for PF0.

Following table shows 4 MB aperture space mapped for PF0 in PCIe config space through BAR0.

Table 141.  Multi Channel DMA CSR Address Space
Address Space Name Range Size Description
QCSR (D2H, H2D) 22’h00_0000 - 22’h0F_FFFF 1MB Individual queue control registers. Up to 2048 D2H and 2048 H2D queues.
MSI-X (Table and PBA) 22’h10_0000 - 22’h1F_FFFF 1MB MSI-X Table and PBA space
GCSR 22’h20_0000 - 22’h2F_FFFF 1MB General DMA control and status registers.
Reserved 22’h30_0000 – 22’h3F_FFFF 1­MB Reserved

Following table shows how QCSR registers for each DMA channel are mapped with 1 MB space of QCSR.

Table 142.  QCSR Address Space
Address Space Name Size DMA Channel Size Description
QCSR (D2H) 512 KB DMA Channel 0 256 B QCSR for DMA channel 0
DMA Channel 1 256 B QCSR for DMA channel 1
…. …. ….
DMA Channel N 256 B QCSR for DMA channel N
QCSR (H2D) 512 KB DMA Channel 0 256 B QCSR for DMA channel 0
DMA Channel 1 256 B QCSR for DMA channel 1
…. …. ….
DMA Channel N 256 B QCSR for DMA channel 2

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