Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 1/14/2022
Public

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8.3.4. Control Message Structure

Both Write back & MSI-X completion modes require the application to register event fds for passing number of completed requests. This is done by passing a control message to the driver through read/write system call. To differentiate between a DMA transfer request submission and a control message, the read/write call for the control message must set the count argument to zero.

Table 133.  Control Message Structure
Structure ctrl_message
uint32_t fefd_tx:1 contains event fd for H2D
uint32_t fefd_rx:1 contains event fd for D2H
uint32_t reserved:30 reserved for future use
int efd_tx; event fd for H2D
int efd_rx; event fd for D2H
int tx_payload; Payload value of Tx Descriptors
int rx_payload; Payload value of Rx Descriptors

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