Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 1/14/2022
Public

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3.8.2.1. D2H Descriptor Format (d2hdm_desc)

Table 28.  D2H Descriptor Format
Name Width Description
SRC_ADDR [63:0] 64

Starting local memory address of allocated transmit buffer read by DMA and instruction must be DMWr for DMA operation with MM_mode=1.

Application specific bit indicates whether this command is an Interrupt.

If App_specific_bit=001, MM_mode=0:
  • Contains the MSI-X PCIe data sent by the external DMA. In this case, PCIe SS doesn’t have the MSI-X enabled. (User MSI-X data). Expectations is for user DMA to use MM_mode=0 and use the DMWr command for both WB and MSI/MSI-X
DEST_ADDR [127:64] 64

Destination system address where the DM sends the data to in the host memory.

When MM_mode=0, instruction is DMWr, app_specific_bits=001
  • Contains the MSI-X PCIe Address sent by the external DMA. In this case, PCIe SS doesn’t have the MSI-X enabled.
  • When app_specific_bits=010, contains the WB address H/L from external DMA’s QCSR
PYLD_CNT [147:128] 20

DMA payload size in bytes. Max 1 MB, with 20’h0 indicating 1 MB

.
DM_FmtType [155:148] 8

‘h60: DMWr

RSVD [159:156] 1

Reserved

PFVF [175:160] 16

{VF_ACTIVE, VFNUM[10:0], PF[3:0]}

MM_mode [176:176] 1

MM_mode=0: Only when MSI-X or Write back is intended. It is illegal and behavior is undefined if a DMRd is instructed with MM_Mode=0;

MM_mode=1: Indication to D2H DM to transfer the data to Host side. MM_mode=1 with DMWr command enables reading local FPGA meory and writing to host memory.

App_specific_bits [179:177] 3

Application-specific bits.

An example use case is that the external DMA controller set these bits to generate the Interrupt. When these bits are set, the MSI-X_en bit should be at 0x0 (default). Otherwise, the behavior is undefined.

DESC_IDX1 [195:180] 16

Unique Identifier for each descriptor, the same ID will be applied AVST source status signaling (d2hdm_desc_status) returning the status of the data mover completion to DMA controller.

MSI-X_en [196:196] 1

Optional. When this bit is set, the external DMA is asking the data mover to generate the MSI-X with the vector number (MSI-X_Vector_num). This can be enabled if and only if data mover is enabled with the parameter INTERRUPT_CTRL=1 at the build time.

You must leave the application specific bits at default 0x0 when optional Interrupt controller is enabled.

Note: This parameter is not supported in the Intel® Quartus® Prime 21.4 release.
MSI-X Vector_num [212:197] 16

This field indicates interrupt vector number. The data mover block reads entry from MSI-X table associated with this vector number and generates MSI-X interrupt towards HOST using the D2H data mover.

DESC_IDX2 [224:213] 12

Optional.

Descriptor ID field providing additional provision for descriptor fetch engine to embed information such as channel number, etc. which the completion status on AVST will return unedited for the response completion packet.

If not used, the user external DMA controller is expected to drive this field to zero. The data mover subsystem will treat the descriptor ID field as {DESC_IDX2, DESC_IDX1}.

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