Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 1/14/2022
Public

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9.1. Queue Control (QCSR)

QCSR space contains queue control and status information. This register space of 1 MB can support up to 2048 H2D and 2048 D2H queues, where each queue is allocated 256 bytes of register space. The memory space allocated to each function is enough for each function to have allocated all the DMA Channels. However, the actual number depends on the parameters input at IP generation time.

Address [7:0] : Registers for the queues

Address [18:8]: Queue number

Address [19]: 0 = D2H, 1=H2D

The following registers are defined for H2D/D2H queues. The base address for H2D and D2H are different, but registers (H2D and D2H) has the same address offsets.

Table 143.  Queue Control Registers
Register Name Address Offset Access Type Description
Q_CTRL 8’h00 R/W Control Register
RESERVED 8’h04 RESERVED
Q_START_ADDR_L 8’h08 R/W Lower 32-bit of queue base address in system memory. This is the beginning of the linked-list of 4KB pages containing the descriptors.
Q_START_ADDR_H 8’h0C R/W Upper 32-bit of queue base address in system memory. This is the beginning of the linked-list of 4KB pages containing the descriptors.
Q_SIZE 8’h10 R/W Number of max entries in a queue. Powers of 2 only.
Q_TAIL_POINTER 8’h14 R/W Current pointer to the last valid descriptor queue entry in the host memory.
Q_HEAD_POINTER 8’h18 RO Current pointer to the last descriptor that was fetched. Updated by Descriptor Fetch Engine.
Q_COMPLETED_POINTER 8’h1C RO Last completed pointer after DMA is done. Software can poll this for status if Writeback is disabled.
Q_CONSUMED_HEAD_ADDR_L 8’h20 R/W Lower 32-bit of the sytem address where the ring consumed pointer is stored. This address is used for comsumed pointer writeback.
Q_CONSUMED_HEAD_ADDR_H 8’h24 R/W Upper 32-bit of the sytem address where the ring consumed pointer is stored. This address is used for comsumed pointer writeback.
Q_BATCH_DELAY 8’h28 R/W Delay the descriptor fetch until the time elapsed from a prior fetch exceeds the delayvalue in this register to maximize fetching efficiency.
RESERVED 8’h2C RESERVED
RESERVED 18’h30 RESERVED
RESERVED 8’h34 RESERVED
Q_DEBUG_STATUS_1 8’h38 RO RESERVED
Q_DEBUG_STATUS_2 8’h3C RO RESERVED
Q_DEBUG_STATUS_3 8’h40 RO RESERVED
Q_PYLD_CNT 8’h44 R/W

20-bit payload count. DMA payload size in bytes. Max 1 MB, with 20’h0 indicating 1 MB. This value has to be same as set in the descriptors payload count field. Applicable only for D2H AVST 1 port mode. Unused in all other modes

Q_RESET 8’h48 R/W Queue reset requested

The following registers are defined for each implemented H2D and D2H queue. The total QCSR address space for each H2D/D2H is 256B and requires 8-bit of address.

Table 144.   Q_CTRL (Offset 8’h0)
Bit [31:0] Name R/W Default Description
[31:10] rsvd Reserved
[9] q_intr_en R/W 0 If set, upon completion generate a MSI-X interrupt.
[8] q_wb_en R/W 0 If set, upon completion, do a write back.
[7:1] rsvd Reserved
[0] q_en R/W 0 Enable. Once it is enabled, the DMA starts fetching pending descriptors and executing them.
Table 145.   Q_START_ADDR_L (Offset 8’h8)
Bit [31:0] Name R/W Default Description
[31:0] q_strt_addr_l R/W 0 After software allocate the descriptor ring buffer, it writes the lower 32-bit allocated address to this register. The descriptor fetch engine use this address and the pending head/tail pointer to fetch the descriptors.
Table 146.   Q_START_ADDR_H (Offset 8’hC)
Bit [31:0] Name R/W Default Description
[31:0] q_strt_addr_h R/W 0 After software allocate the descriptor ring buffer, it writes the upper 32-bit allocated address to this register. The descriptor fetch engine use this address and the pending head/tail pointer to fetch the descriptors.
Table 147.   Q_SIZE (Offset 8’h10)
Bit [31:0] Name R/W Default Description
[31:5] rsvd Reserved
[4:0] q_size R/W 1 Size of the descriptor ring in power of 2 and max value of 16. The unit is number of descriptors. Hardware defaults to using a value of 1 if an illegal value is written. A value of 1 means queue size of 2 (2^1). A value is 16 (0x10) means queue size of 64K (2^16).
Table 148.   Q_TAIL_POINTER (Offset 8’h14)
Bit [31:0] Name R/W Default Description
[31:16] rsvd Reserved
[15:0] q_tl_ptr R/W 0 After software sets up a last valid descriptor in the descriptor buffer, it programs this register with the position of the last (tail) valid descriptor that is ready to be executed. The DMA Descriptor Engine fetches descriptors from the buffer upto this position of the buffer
Table 149.   Q_HEAD_POINTER (Offset 8’h18)
Bit [31:0] Name R/W Default Description
[31:16] rsvd Reserved
[15:0] q_hd_ptr R/W 0 After DMA Descriptor Fetch Engine fetches the descriptors from the descriptor buffer, upto the tail pointer, it updates this register with that last fetched descriptor position. The fetch engine only fetches descriptors if the head and tail pointer is not equal.
Table 150.   Q_COMPLETED_POINTER (Offset 8’h1C)
Bit [31:0] Name R/W Default Description
[31:16] rsvd Reserved
[15:0] q_cmpl_ptr R/W 0 This register is updated by hardware to store the last descriptor position (pointer) that DMA has completed, that is all data for that descriptor and previous descriptors have arrived at the intended destinations. Software can poll this register to find out the status of the DMA for a specific queue.
Table 151.   Q_CONSUMED_HEAD_ADDR_L (Offset 8’h20)
Bit [31:0] Name R/W Default Description
[31:0] q_cnsm_hd_addr_l R/W 0 Software programs this register with the lower 32-bit address location where the writeback targets after DMA is completed for a set of descriptors.
Table 152.   Q_CONSUMED_HEAD_ADDR_H (Offset 8’h24)
Bit [31:0] Name R/W Default Description
[31:0] q_cnsm_hd_addr_h R/W 0 Software programs this register with the upper 32-bit address location where the writeback targets after DMA is completed for a set of descriptors.
Table 153.   Q_BATCH_DELAY (Offset 8’h28)
Bit [31:0] Name R/W Default Description
[31:20] rsvd Reserved
[19:0] q_batch_dscr_delay R/W 0 Software programs this register with the the amount of time between fetches for descriptors. Each unit is 2ns.
Table 154.   Q_PYLD_CNT register (offset 8'h44)
Bit [31:0] Name R/W Default Description
[31:20] rsvd Reserved
[19:0] q_pyld_cnt R/W 0

20-bit payload count. DMA payload size in bytes. Max 1 MB, with 20’h0 indicating 1 MB. This value has to be same as set in the descriptors payload count field. Applicable only for D2H AVST 1 port mode. Unused in all other modes

Table 155.   Q_RESET (Offset 8’h48)
Bit [31:0] Name R/W Default Description
[31:1] rsvd Reserved
[0] q_reset R/W 0 Request reset for the queue by writing 1’b1 to this register, and poll for value of 1’b0 when reset has been completed by hardware. Hardware clears this bit after completing the reset of a queue.

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