Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 1/14/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.3. Resets

Table 32.  Multi Channel DMA IP for PCI Express Reset Signals
Signal Name I/O Type Description
H-Tile
pin_perst_n Input This is an active-low input to the PCIe Hard IP, and implements the PERST# function defined by the PCIe specification.
npor Input Application drives this active-low reset input to the PCIe Hard IP. This resets entire PCIe Hard IP. If not used, you must tie this input to 1.
app_nreset_status Output

This is an active low reset status. This is deasserted after the PCIe Hard IP has come out of reset.

ninit_done Input

This is an active low input signal. A "1" indicates that the FPGA device is not yet fully configured.

A "0" indicates the device has been configured and is in normal operating mode.

To use the ninit_done input, instantiate the Reset Release Intel FPGA IP in your design and use its ninit_done output. The Reset Release IP is required in Intel Stratix 10 design. It holds the Multi Channel DMA for PCI Express IP in reset until the FPGA is fully configured and has entered user mode.

P-Tile and F-Tile
pin_perst_n Input See H-Tile pin_perst description
ninit_done Input See H-Tile ninit_done description
app_rst_n Output

Resets MCDMA soft IP blocks and user logic. app_rst_n is asserted when software writes to SW_RESET register bit[0].

p0_pld_link_req_rst_o Output Warm reset request to application
p0_pld_warm_rst_rdy_i Input Warm reset ready from application

Did you find the information on this page useful?

Characters remaining:

Feedback Message