Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 1/14/2022

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Document Table of Contents

6. Parameters (P-Tile and F-Tile)

This chapter provides a reference for all the P-Tile and F-Tile parameters of the Multi Channel DMA IP for PCI Express.

Table 65.  Design Environment ParameterStarting in Intel® Quartus® Prime 18.0, there is a new parameter Design Environment in the parameters editor window.




Design Environment



Identifies the environment that the IP is in.

  • The Standalone environment refers to the IP being in a standalone state where all its interfaces are exported.
  • The System environment refers to the IP being instantiated in a Platform Designer system.