Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 1/14/2022
Public

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8.2.6. API Flow

The flow between the Host software components and hardware components is depicted in below sequence diagram for Host to Device data transfer.

Figure 40. Host to Device Sequence

The flow between the Host software components and hardware components is depicted in below sequence diagram for Device to Host data transfer.

Figure 41. Device to Host Sequnece

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