Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 1/14/2022
Public

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3.1.6.3. Packet (File) Boundary

When streaming the DMA data, the packet (file) boundary is indicated by the SOF and EOF bits of the descriptor and corresponding sof and eof signals of the Avalon-ST interface. Channel interleaving is not supported. A channel switch on AVST interface can only happen on packet boundary

Table 19.  Multi Channel DMA Streaming Packet Boundary<n>: 0-3 for 4 ports, 0 for 1 port
Packet Boundary Descriptor Field AVST Source (H2D) Signal AVST Sink (D2H) Signal
Start of Packet SOF h2d_st_sof_<n>_o d2h_st_sof_<n>_i
End of Packet EOF h2d_st_eof_<n>_o d2h_st_sof_<n>_i

In Avalon-ST 1 port mode, a channel switch can only happen at packet boundary.

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