Intel® Stratix® 10 Configuration User Guide

ID 683762
Date 9/21/2023
Document Table of Contents Designing with the PFL II IP Core for Avalon-ST Single Device Configuration

This section describes the procedures on how to use the PFL II IP core.

To target a MAX® II, MAX® V, or Intel® MAX® 10 device requires the use of Intel® Quartus® Prime Standard Edition whereas targeting a Intel® Stratix® 10 requires Intel® Quartus® Prime Pro Edition.

The process of creating the Avalon-ST single device configuration design targeting a MAX10/MAX V/MAX II device involves three steps.
  1. Generate the AVST design for the MAX device with the default option address.
  2. Create the Intel® Stratix® 10 .pof file in setting the appropriate option bits.
  3. Regenerate the Parallel Flash Loader II Intel FPGA IP (PFL II) with the option bits used to generate the Intel® Stratix® 10 .pof file and recompile the Intel® MAX® 10 design.

You can find a MAX® V system design example that implements the PFL II IP for AVST x16 configuration mode in the installer package of the Intel® Stratix® 10 GX FPGA Development Kit.

Figure 26. Process for Using the PFL IP CoreFigure shows the process for using the PFL IP core, using MAX® II as an example.

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