Intel Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit User Guide

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ID 683752
Date 4/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Powering Up the Development Kit 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Revision History A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Intel® Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Powering Up the Development Kit x
3.1. Default Settings 3.2. Power Up 3.3. Perform board restore
3.3. Perform board restore x
3.3.1. Restore board System Intel® MAX® 10 with default factory image 3.3.2. Restore board QSPI flash with the default factory image
4. Board Test System x
4.1. Setting Up the BTS GUI Running Environment 4.2. Test the functionality of the Development Kits 4.3. Control on-board clock through Clock Controller GUI 4.4. Control on-board power regulator through Power Monitor GUI
4.1. Setting Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Installing the Quartus Prime Software 4.1.5. Running the BTS GUI
4.2. Test the functionality of the Development Kits x
4.2.1. The Configure Menu 4.2.2. The Sys Info Tab 4.2.3. The GPIO Tab 4.2.4. The XCVR Tab 4.2.5. The DDR4 Tab 4.2.6. The SSS Tab 4.2.7. The EEPROM Tab
5. Development Kit Hardware and Configuration x
5.1. Configure FPGA and access HPS Debug Access Port by JTAG 5.2. Configure the FPGA device by AS modes (Default Mode) 5.3. Configure the FPGA device by AvST modes 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card 5.4.2. HPS NAND Daughter Card
6. Custom Projects for the Development Kit x
6.1. Add SmartVID settings in Intel® Quartus® Prime QSF file 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Powering Up the Development Kit
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Revision History
A. Development Kit Components
B. Additional Information

A.5. Memory Interfaces

FPGA dedicated external memory interface (SO-DIMM)

Intel is designing and verifying a customized QDRIV SODIMM module which fits with the 260-pin DDR4 SODIMM socket. Both DDR4 and QDRIV protocols can be tested on one single socket CON1. A long guide pin assembled on the customized QDRIV module slides in the guide hole which is reserved on Intel Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit. This mechanical design avoids a wrong plug between customized QDRIV SODIMM and unsupported mother board. Only Intel Agilex® 7 FPGA fabric can access this external memory interface.

FPGA and HPS shared external memory interface (DDR4)

DDR4 component interface is a 72 bit, single rank configuration based on x16 component. It runs at 2400 Mbps. Footprint supports both MT40A1G16RC-062E and MT40A1G16KNR-062E component. By default, the component is: MT40A1G16RC-062E. Both Intel Agilex® 7 FPGA fabric and HPS can access this external memory interface, however they cannot be accessed at the same time.

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