Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit User Guide

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ID 683752
Date 11/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit User Guide A. Development Kit Components B. AG 7 FPGA F-Series XCVR-SoC DK Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Altera® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board System MAX® 10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. Test the Functionality of the Development Kits 4.3. Control Onboard Clock through Clock Controller GUI 4.4. Control Onboard Power Regulator through Power Monitor GUI
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. Test the Functionality of the Development Kits x
4.2.1. The Configure Menu 4.2.2. The Sys Info Tab 4.2.3. The GPIO Tab 4.2.4. The XCVR Tab 4.2.5. The DDR4 Tab 4.2.6. The SSS Tab 4.2.7. The EEPROM Tab
5. Development Kit Hardware and Configuration x
5.1. Configuring FPGA Device and Accessing HPS Debug Access Port by JTAG 5.2. Configuring FPGA Device by AS Modes (Default Mode) 5.3. Configuring FPGA Device by AvST Modes 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card 5.4.2. HPS NAND Daughter Card
6. Custom Projects for the Development Kit x
6.1. Adding SmartVID settings in Quartus® Prime QSF file 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit User Guide
A. Development Kit Components
B. AG 7 FPGA F-Series XCVR-SoC DK Developer Resources
C. Safety and Regulatory Compliance Information

A.1. System Management

Two MAX® 10 FPGAs (10M16SCU324C8G) are used for system management. The system MAX® 10 acts as system controller. It handles FPGA AvST configuration, I2C bus access, fan speed control, and system reset functions. The UB2/PWR MAX® 10 acts as power manager and onboard JTAG controller. Refer to below description for each function:
  • Power management: Controls systems and FPGA power up and optional down sequence, supervises power regulators/switches status and manages power faults, supervises temperature ADC interrupt signals, and manages temperature faults.
  • JTAG controller: Manages JTAG chain topology, JTAG master source and JTAG slaves by SW3.
Table 7.  JTAG Master Sources
Schematic Signal Name Description
EXT_JTAG_TCK/TDO/TMS/TDI JTAG header J19 for Intel® download cable
FX2_Dp/n Input port CN1 for onboard Intel® download circuit
HPS_GPIO[32:35] Mictor 38 pin header on OOBE daughter card

The Agilex™ 7 HPS JTAG slave can be accessed from either SDM dedicated JTAG pins or HPS dedicated I/Os. When it is accessed from SDM JTAG pins (FPGA_JTAG_TCK/TDO/TMS/TDI), SDM is chained with HPS inside FPGA part. When it is accessed from HPS dedicated I/Os (HPS_GPIO[32:35]), HPS is chained externally by PCB traces.

Table 8.  JTAG Chain Topology Settings
Mode SW3 [8:6] SW3[5][2][1]

ON: Bypass from chain

OFF: Enable in chain

 Function
000

ON/ON/ON

(Default)

SW3.1 (SDM+HPS)

SW3.2 (SysMAX)

SW3.5 ( PCIe* )

Mode 1: Onboard Intel® download circuit act as the only JTAG Master

Chained HPS with SDM nodes internally

Mode 3: External Intel® download cable act as the only JTAG Master

Chained HPS with SDM nodes internally
001 ON/ON/OFF

SDM is always enabled in the JTAG chain

SW3.1 (HPS)

SW3.2 (SysMAX)

SW3.5 ( PCIe* )

Mode 2: Onboard Intel® download circuit act as the only JTAG Master

Chained HPS with SDM nodes externally

Mode 4: External Intel® download cable act as the only JTAG Master

Chained HPS with SDM node externally
100 OFF/ON/ON

SW3.1 (SDM)

SW3.2 (SysMAX)

SW3.5 ( PCIe* )

Mode 7: Both onboard Intel® download circuit and OOBE act as JTAG Masters

Separated HPS and SDM JTAG chains, OOBE only drive HPS

Mode 8: Both external Intel® download cable and OOBE JTAG act as JTAG Masters

Separated HPS and SDM JTAG chains, OOBE only drive HPS
110 OFF/OFF/ON —

Mode 11: Both onboard Intel® download circuit and OOBE act as JTAG Masters

Onboard Intel® download circuit only drive SDM, OOBE only drive HPS
Others — — Reserved
Note: UB2/PWR MAX® 10 has dedicated JTAG header J18 onboard bottom side. When you plug in the Intel® FPGA Download Cable dongle cable into J18, power MAX® 10 enters debug mode 0 or 1 by detecting the PWRMAX_DEBUGMDn signals. You should not overwrite UB2/ MAX® 10 image through J18, otherwise the board cannot function properly.
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