Intel® Agilex™ F-Series Transceiver-SoC Development Kit User Guide

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ID 683752
Date 6/21/2022
Public
Document Table of Contents

A.1. System Management

Two Intel® MAX® 10 FPGAs (10M16SCU324C8G) are used for system management. System Intel® MAX® 10 acts as system controller. It handles FPGA AvST configuration, I2C bus access, fan speed control and system reset functions. The UB2/PWR Intel® MAX® 10 acts as Power manager and on-board JTAG controller. Refer to below description for each function:
  • Power management: control systems and FPGA power up and optional down sequence, supervise power regulators/switches status and manage power faults, supervise temperature ADC interrupt signals and manage temperature faults.
  • JTAG controller: Manage JTAG chain topology, JTAG master source and JTAG slaves by SW3
Table 8.  JTAG Master Sources
Schematic Signal Name Description
EXT_JTAG_TCK/TDO/TMS/TDI JTAG header J19 for Intel download cable
FX2_Dp/n input port CN1 for on-board Intel download circuit
HPS_GPIO[32:35] Mictor 38pin header on OOBE daughter card

Intel® Agilex™ HPS JTAG slave can be accessed from either SDM dedicated JTAG pins or HPS dedicated I/Os. When it is accessed from SDM JTAG pins (FPGA_JTAG_TCK/TDO/TMS/TDI), SDM is chained with HPS inside FPGA part. When it is accessed from HPS dedicated I/Os (HPS_GPIO[32:35]), HPS is chained externally by PCB traces.

Table 9.  JTAG Chain Topology Settings
Mode SW3 [8:6] SW3 [5] [2] [1]

ON: Bypass from chain

OFF: Enable in chain

Function
000

ON/ON/ON

(Default)

SW3.1 (SDM+HPS)

SW3.2 (SysMAX)

SW3.5 (PCIe)

Mode 1: On-board Intel download circuit act as the only JTAG Master

Chained HPS with SDM nodes internally

Mode 3: External Intel download cable act as the only JTAG Master

Chained HPS with SDM nodes internally

001 ON/ON/OFF

SDM is always enabled in the JTAG chain

SW3.1 (HPS)

SW3.2 (SysMAX)

SW3.5 (PCIe)

Mode 2: On-board Intel download circuit act as the only JTAG Master

Chained HPS with SDM nodes externally

Mode 4: External Intel download cable act as the only JTAG Master

Chained HPS with SDM node externally

100 OFF/ON/ON

SW3.1 (SDM)

SW3.2 (SysMAX)

SW3.5 (PCIe)

Mode 7: Both On-board Intel download circuit and OOBE act as JTAG Masters

Separated HPS and SDM JTAG chains, OOBE only drive HPS

Mode 8: Both External Intel download cable & OOBE JTAG act as JTAG Masters

Separated HPS and SDM JTAG chains, OOBE only drive HPS

110 OFF/OFF/ON N/A

Mode 11: Both On-board Intel download circuit and OOBE act as JTAG Masters

On-board Intel download circuit only drive SDM, OOBE only drive HPS

Others N/A N/A Reserved
Note: UB2/PWR Intel® MAX® 10 has dedicated JTAG header J18 on board bottom side. When customer plugs in the Intel® FPGA Download Cable dongle cable into J18, power Intel® MAX® 10 enters debug mode 0 or 1 by detecting PWRMAX_DEBUGMDn signals. You should not overwrite UB2/ Intel® MAX® 10 image through J18, otherwise board will not function properly.

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