Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit User Guide

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ID 683752
Date 11/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit User Guide A. Development Kit Components B. AG 7 FPGA F-Series XCVR-SoC DK Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Altera® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board System MAX® 10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. Test the Functionality of the Development Kits 4.3. Control Onboard Clock through Clock Controller GUI 4.4. Control Onboard Power Regulator through Power Monitor GUI
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. Test the Functionality of the Development Kits x
4.2.1. The Configure Menu 4.2.2. The Sys Info Tab 4.2.3. The GPIO Tab 4.2.4. The XCVR Tab 4.2.5. The DDR4 Tab 4.2.6. The SSS Tab 4.2.7. The EEPROM Tab
5. Development Kit Hardware and Configuration x
5.1. Configuring FPGA Device and Accessing HPS Debug Access Port by JTAG 5.2. Configuring FPGA Device by AS Modes (Default Mode) 5.3. Configuring FPGA Device by AvST Modes 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card 5.4.2. HPS NAND Daughter Card
6. Custom Projects for the Development Kit x
6.1. Adding SmartVID settings in Quartus® Prime QSF file 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit User Guide
A. Development Kit Components
B. AG 7 FPGA F-Series XCVR-SoC DK Developer Resources
C. Safety and Regulatory Compliance Information

4.4. Control Onboard Power Regulator through Power Monitor GUI

The Power Monitor GUI reports most power rails voltage, current, and power information on the board. You can fine tune some regulators’ output voltage by Power Monitor GUI. It also collects temperature from FPGA SDM, FPGA core, E-Tile, P-Tile, power modules, and diode assembled on PCB.

The Power Monitor GUI communicates with system MAX® 10 through either USB port CN1 or J19. System MAX® 10 monitors and controls power regulator, temperature/voltage/current sensing chips through a 2-wire serial bus.

The instructions to run Power Monitor GUI are stated in the Running the BTS GUI section. Alternatively, you can start using the Power Monitor feature by selecting the Power icon on the BTS GUI.

Attention: You cannot run the stand-alone power application when BTS or Clock Controller GUI is running at the same time.
Figure 21. Power Monitor GUI - 1 for Power Solution 2 Board (DK-SI-AGF014EB)
Figure 22. Power Monitor GUI - 2 for Power Solution 2 Board (DK-SI-AGF014EB)
Figure 23. Power Monitor GUI - 3 for Power Solution 2 Board (DK-SI-AGF014EB)
Figure 24. Power Monitor GUI - 4 for Power Solution 2 Board (DK-SI-AGF014EB)
Figure 25. Power Monitor GUI - 1 for Power Solution 1 Board (DK-SI-AGF014EA and DK-SI-AGF014E3ES)
Figure 26. Power Monitor GUI - 2 for Power Solution 1 Board (DK-SI-AGF014EA and DK-SI-AGF014E3ES)
Figure 27. Power Monitor GUI - 3 for Power Solution 1 Board (DK-SI-AGF014EA and DK-SI-AGF014E3ES)
Figure 28. Power Monitor GUI - 4 for Power Solution 1 Board (DK-SI-AGF014EA and DK-SI-AGF014E3ES)

The following sections describe the Power Monitor buttons.

Configuration

  • Speed Adjustment: Adjusts the update rate of current curve.
  • Select Data Source: Switches between different monitor targets.
  • VOUT Adjustment (mV): Fine tunes each smart regulator module output within ±7% range. Select Power Rail, fill in the box, and press the Set button.

Temperature

  • Board: PCB surface temperature near U31.
  • SDM/E-tile/P-tile/Core: FPGA die internal temperature sense diode (TSD).
  • QSFP: Diode assembled on PCB and close to QSFP/QSFPDD modules.
  • VID_1/VCCH/3.3V/VCCPT/VCCIO: Regulator U54/U57/U53/U58/U59 internal TSD. No onboard current measurement circuit for 3.3V_PRE, 5V, VCC_BIAS, 1.8V, 2.5V, and 1.2V.
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