Intel Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit User Guide

ID 683752
Date 4/21/2023
Document Table of Contents

4.2.5. The DDR4 Tab

The DDR4 tab allows you to read and write DDR4 memory on your board. Plug the DDR4 SODIMM module to single socket CON1, then download EMIF designs through BTS.

Figure 14. The DDR4 Tab

The following sections describe the controls on the DDR4 tab.


Initiates DDR4 memory transaction performance analysis.


Terminates transaction performance analysis.

Performance Indicators

These controls display current transaction performance analysis information collected since you last clicked Start:
  • Write, Read and Total performance bars: Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve.
  • Write (MBps), Read (MBps) and Total (MBps): Show the number of bytes analyzed per second.
  • Data Bus: 72 bits(8 bits ECC) wide, reference clock is 100 MHz and the frequency is 1200 MHz double data rate 2400 MT/s.

Error Control

This control displays data errors detected during analysis and allows you to insert errors:
  • Detected Errors: Displays the number of data errors detected in the hardware.
  • Inserted Errors: Displays the number of errors inserted into the transaction stream.
  • Insert: Inserts a one-word error into the transaction stream each time you click the button. Insert Error is only enabled during transaction performance analysis.
  • Clear: Resets the detected error and inserted error counters to zeroes.

Address Range (Bytes)

Determines the number of addresses to use in each iteration of reads and writes.

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