Intel Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit User Guide

ID 683752
Date 4/21/2023
Document Table of Contents
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5.1. Configure FPGA and access HPS Debug Access Port by JTAG

  1. JTAG access does not rely on SW1 settings and system image.
  2. Plug the USB cable to CN1 or Intel® FPGA Download Cable to J19.
  3. Open Intel® Quartus® Prime Programmer, system console to configuration Intel Agilex® 7 FPGA SDM, system Intel® MAX® 10 and PCIe JTAG nodes.
  4. Open Arm* Development Studio 5* (DS-5*) Intel SoC FPGA Edition to connect to and communicate with the HPS Debug Access Port (DAP) through the same JTAG interface.
    Note: By default, HPS and FPGA SDM JTAG nodes are chained together internally. SW3.1 bypasses or enables both nodes at the same time. OOBE’s Mictor 38-pin header cannot access HPS DAP function.

    If attestation and/or Black Key Provisioning (BKP) is enabled on the Intel Agilex® 7 device, you must use the updated SDM firmware and TCK guidelines (JTAG clock).

    • You must update to the SDM firmware delivered with the Intel® Quartus® Prime Pro Edition version 21.3 and beyond.
    • For the TCK pin, you must either leave the TCK pin unconnected, or connect the TCK pin to the VCCIO_SDM supply using a 10-kΩ pull-up resistor.
    Note: The existing guidance in the Intel Agilex® 7 Device Family Pin Connection Guidelines to connect TCK to a 1-kΩ pull-down resistor is included for noise suppression. The change in guidance to a 10-kΩ pull-up resistor is not expected to affect the device functionally.

    For more information about connecting the TCK pin, refer to the Intel Agilex® 7 Device Family Pin Connection Guidelines.