Intel® Agilex™ F-Series Transceiver-SoC Development Kit User Guide

ID 683752
Date 6/21/2022
Public
Document Table of Contents

5.3. Configure the FPGA device by AvST modes

  1. Set SW1 to AvST x32 mode first.
  2. Plug SDM QSPI flash daughter into J11.
  3. Default system Intel® MAX® 10 image support AvST x32 mode only. You should build a corresponding .POF image if you select AvST x8 or AvST x16 configuration mode.
  4. Detect QSPI flash in Programmer and program QSPI flash with factory provided AvST x32 test image file. Power cycle the board, use push button S17 to choose page, and S18 to configure FPGA. LED_D27, LED_28, LED_29 are used to indicate the active page.
    Table 6.  AvST x32 LED Behavior
    LED Page0 (XCVR) Page1 (DDR4) Page2 (SSS) Page3 (GPIO)
    LED_D27 ON OFF OFF OFF
    LED_D28 OFF ON OFF ON
    LED_D29 OFF OFF ON ON
    FPGA_LED_G[0] Blinking Blinking OFF/Blinking ON
    FPGA_LED_G[1] ON OFF OFF/Blinking ON
    FPGA_LED_G[2] ON ON OFF/Blinking ON
    FPGA_LED_G[3] ON OFF Blinking ON
    FPGA_LED_G[4] OFF OFF OFF ON
    FPGA_LED_G[5] OFF OFF OFF ON
    FPGA_LED_G[6] OFF OFF OFF ON
    FPGA_LED_G[7] OFF OFF OFF ON

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