Intel Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit User Guide

Download PDF
ID 683752
Date 4/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Powering Up the Development Kit 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Revision History A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Intel® Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Powering Up the Development Kit x
3.1. Default Settings 3.2. Power Up 3.3. Perform board restore
3.3. Perform board restore x
3.3.1. Restore board System Intel® MAX® 10 with default factory image 3.3.2. Restore board QSPI flash with the default factory image
4. Board Test System x
4.1. Setting Up the BTS GUI Running Environment 4.2. Test the functionality of the Development Kits 4.3. Control on-board clock through Clock Controller GUI 4.4. Control on-board power regulator through Power Monitor GUI
4.1. Setting Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Installing the Quartus Prime Software 4.1.5. Running the BTS GUI
4.2. Test the functionality of the Development Kits x
4.2.1. The Configure Menu 4.2.2. The Sys Info Tab 4.2.3. The GPIO Tab 4.2.4. The XCVR Tab 4.2.5. The DDR4 Tab 4.2.6. The SSS Tab 4.2.7. The EEPROM Tab
5. Development Kit Hardware and Configuration x
5.1. Configure FPGA and access HPS Debug Access Port by JTAG 5.2. Configure the FPGA device by AS modes (Default Mode) 5.3. Configure the FPGA device by AvST modes 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card 5.4.2. HPS NAND Daughter Card
6. Custom Projects for the Development Kit x
6.1. Add SmartVID settings in Intel® Quartus® Prime QSF file 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Powering Up the Development Kit
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Revision History
A. Development Kit Components
B. Additional Information

1.2. Feature Summary

  • Intel Agilex® 7 FPGA F-Series, 1400 KLE, 2486A package
  • 16 E-tile transceiver channels fan out to Multi-Speed Port (MXP), Quad Small Form Factor Double Density (QSFPDD) and Quad Small Form-Factor Pluggable 28 (QSFP28) interfaces
  • 16 P-tile channels fan out to PCIe Root complex interface which can run up to Gen4 depending on FPGA core fabric speed grade
  • 8 GB Double Data Rate 4 (DDR4) component interface for either FPGA fabric or HPS
  • Small Outline Dual In-line Memory Module (SODIMM) interface for single-rank DDR4 and customized QDRIV/RLDRAM3 modules
  • IO48 interface for HPS OOBE (Out of Box Experience) and NAND daughter cards
  • Flash slot 1 interface for Queued Serial Peripheral Interface (QSPI) and Secure Digital and MultiMediaCard (SDMMC) flash daughter cards (AS and SD/MMC configuration modes)
  • Flash slot 2 interface for QSPI and CFI NOR flash daughter cards (AvST configuration mode)
  • Dual-channel network synchronizer clock circuit for both Synchronous Ethernet and IEEE 1588
Level Two Title