Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit User Guide

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ID 683752
Date 11/12/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit User Guide A. Development Kit Components B. AG 7 FPGA F-Series XCVR-SoC DK Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Altera® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board System MAX® 10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. Test the Functionality of the Development Kits 4.3. Control Onboard Clock through Clock Controller GUI 4.4. Control Onboard Power Regulator through Power Monitor GUI
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. Test the Functionality of the Development Kits x
4.2.1. The Configure Menu 4.2.2. The Sys Info Tab 4.2.3. The GPIO Tab 4.2.4. The XCVR Tab 4.2.5. The DDR4 Tab 4.2.6. The SSS Tab 4.2.7. The EEPROM Tab
5. Development Kit Hardware and Configuration x
5.1. Configuring FPGA Device and Accessing HPS Debug Access Port by JTAG 5.2. Configuring FPGA Device by AS Modes (Default Mode) 5.3. Configuring FPGA Device by AvST Modes 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card 5.4.2. HPS NAND Daughter Card
6. Custom Projects for the Development Kit x
6.1. Adding SmartVID settings in Quartus® Prime QSF file 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit User Guide
A. Development Kit Components
B. AG 7 FPGA F-Series XCVR-SoC DK Developer Resources
C. Safety and Regulatory Compliance Information

A.7. Daughter Cards

HPS IO48 OOBE Daughter Card

  • One RGMII 10/100/1000 Mbps Ethernet port: Standard RJ-45
  • One UART port: Standard USB Mini-B Receptacle
  • One Micro SD card connector: Standard Micro SD card socket
  • One USB 2.0 port: Standard USB Micro-AB Receptacle
  • One Mictor 38-pin connector (JTAG only without Trace signals)
  • HPS dedicated JTAG pins are connected with both mother board JTAG chain and Mictor 38 pin header
  • I2C: HPS I2C port
  • GPIO
    • 2 push buttons
    • 3 LEDs
    • 1 Ethernet Interrupt from Ethernet PHY
    • 1 USB over-current indicator
  • HPS Clock: 25 MHz oscillator

HPS IO48 NAND Daughter Card

  • One RGMII 10/100/1000 Mbps Ethernet port: Standard RJ-45
  • One UART port: Standard USB Mini-B Receptacle
  • NAND Flash (x16): 8 Gb
  • eMMC (x8): 8 GB 5.0 compliant eMMC
  • I2C: HPS I2C port
  • GPIO
    • 2 push buttons
    • 3 LEDs
    • 1 Ethernet Interrupt from Ethernet PHY
  • HPS Clock: 25 MHz oscillator

256 MB QSPI Flash Daughter Card

This daughter card is pre-programmed with GHRD for AS configuration. It can be re-programmed by user image or factory provided AvST test image for AvST configuration mode. The part number is MT25QU02GCBB8E12-0SIT.

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