Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit User Guide

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ID 683752
Date 11/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit User Guide A. Development Kit Components B. AG 7 FPGA F-Series XCVR-SoC DK Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Altera® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board System MAX® 10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. Test the Functionality of the Development Kits 4.3. Control Onboard Clock through Clock Controller GUI 4.4. Control Onboard Power Regulator through Power Monitor GUI
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. Test the Functionality of the Development Kits x
4.2.1. The Configure Menu 4.2.2. The Sys Info Tab 4.2.3. The GPIO Tab 4.2.4. The XCVR Tab 4.2.5. The DDR4 Tab 4.2.6. The SSS Tab 4.2.7. The EEPROM Tab
5. Development Kit Hardware and Configuration x
5.1. Configuring FPGA Device and Accessing HPS Debug Access Port by JTAG 5.2. Configuring FPGA Device by AS Modes (Default Mode) 5.3. Configuring FPGA Device by AvST Modes 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card 5.4.2. HPS NAND Daughter Card
6. Custom Projects for the Development Kit x
6.1. Adding SmartVID settings in Quartus® Prime QSF file 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit User Guide
A. Development Kit Components
B. AG 7 FPGA F-Series XCVR-SoC DK Developer Resources
C. Safety and Regulatory Compliance Information

3.1. Default Settings

The Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit ships with its board switches preconfigured to support the design examples in the kit. If you suspect your board might not be correctly configured with the default settings, follow the instructions in the factory default switch settings table to return to its factory settings before proceeding ahead.
Note: "X" refers to Don't Care in the table below.
Table 4.  Factory Default Switch Settings
Switch Default Position Default Function
SW1[1:4] ON/OFF/OFF/X

Configuration mode setting bits

AS - Normal mode
SW2[1:8] X/X/X/X/X/X/X/X

FPGA user DIP switch
SW3[1:8] OFF/OFF/X/X/ON/ON/ON/ON

6:8—JTAG chain setting bits

FPGA SDM and HPS are chained internally

1:5—JTAG slave node bypass control

The FPGA SDM/HPS and the system MAX® 10 are in the JTAG chain

PCIe* is bypassed
SW4[1:4] X/OFF/OFF/OFF

UB2/PWR MAX® 10 pin strap settings

2—VCCFUSEWR_SDM_FPGA_2.4V rail is set to 1.8 V

3—Regulator U60 drive VCCL_HPS_FPGA_0.9V rail. Turn off U60 by this DIP switch bit as this rail source from VCC_FPGA_VID

4—LMK05028 is active by default
SW5[1:4] OFF/OFF/X/X

System MAX® 10 pin strap settings

1—Factory Load = 0

2—Si549 instead of SMA connectors supply clock to Si53311
SW6[1:4] OFF/OFF/OFF/X

FPGA core regulators’ I2C bus chain settings

1:3—Core regulators’ I2C bus is isolated from main I2C bus
SW8 OFF Power slide switch
SW10[1:2] OFF/ON

System MAX® 10 pin strap settings

1—I2C_3.3V_EN is high by default

2—CLKCleaner_IO_TSn is low
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