Intel® Agilex™ F-Series Transceiver-SoC Development Kit User Guide

ID 683752
Date 9/30/2022
Public
Document Table of Contents

3.1. Default Settings

The Intel® Agilex™ F-Series Transceiver-SoC Development Kit ships with its board switches preconfigured to support the design examples in the kit. If you suspect your board might not be correctly configured with the default settings, follow the instructions in the factory default switch settings table to return to its factory settings before proceeding ahead.

Note: X refers to Don't Care in the table below.
Table 4.  Factory Default Switch Settings
Switch Default Position Default Function
SW1 [1:4] ON/OFF/OFF/X

Configuration mode setting bits

AS - Normal mode

SW2 [1:8] X/X/X/X/X/X/X/X

FPGA user dipswitch

SW3 [1:8] OFF/OFF/X/X/ON/ON/ON/ON

6:8 - JTAG chain setting bits

FPGA SDM and HPS are chained internally

1:5 - JTAG slave node bypass control

FPGA SDM/HPS and system Intel® MAX® 10 are in JTAG chain

PCIe is bypassed

SW4 [1:4] X/OFF/OFF/OFF

UB2/PWR Intel® MAX® 10 Pin Strap Settings

2 - VCCFUSEWR_SDM_FPGA_2.4V rail is set to 1.8 V

3 - Regulator U60 drive VCCL_HPS_FPGA_0.9V rail. Turn off U60 by this dipswitch bit as this rail source from VCC_FPGA_VID

4 - LMK05028 is active by default

SW5 [1:4] OFF/OFF/X/X

System Intel® MAX® 10 Pin Strap Settings

1 - Factory Load = 0

2 - Si549 instead of SMA connectors supply clock to Si53311

SW6 [1:4] OFF/OFF/OFF/X

FPGA core regulators’ I2C bus chain settings

1:3 - Core regulators’ I2C Bus is isolated from main I2C bus

SW8 OFF

Power slide switch

SW10 [1:2] OFF/ON

System Intel® MAX® 10 Pin Strap Settings

1 - I2C_3.3V_EN is high by default

2 - CLKCleaner_IO_TSn is low

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