|Schematic Signal Name
The LMK05028 device is a high-performance clock generator, jitter cleaner and clock synchronizer with advanced reference clock selection and hitless switching to meet the stringent requirements of communications infrastructure applications. This clock device has two independent PLL cores that can each synchronize or lock to one of four reference clock inputs, and it can generate up to eight output clocks with up to six different frequencies.
Two E-tile transceiver recovery clocks (Cleaner_RECOVERY_p/n [0:1]) feed two of four reference clock inputs, single-end and differential SMA clocks feed other two inputs. LMK05028’s output clocks feed back to E-tile transceiver bank, general I/O banks and SMA connectors. LMK05028 can be set to power down mode by SW4.4.
Intel Agilex® 7 FPGA F-Series manages LMK05028 through general purpose I/Os (Cleaner_GPIO[0:6], Cleaner_INSEL, Cleaner SCL/SDA, Cleaner_status[0:1]). The connection between these general purpose IOs and FPGA can be shut down by SW10.2.