Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit User Guide

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ID 683752
Date 11/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit User Guide A. Development Kit Components B. AG 7 FPGA F-Series XCVR-SoC DK Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Altera® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board System MAX® 10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. Test the Functionality of the Development Kits 4.3. Control Onboard Clock through Clock Controller GUI 4.4. Control Onboard Power Regulator through Power Monitor GUI
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. Test the Functionality of the Development Kits x
4.2.1. The Configure Menu 4.2.2. The Sys Info Tab 4.2.3. The GPIO Tab 4.2.4. The XCVR Tab 4.2.5. The DDR4 Tab 4.2.6. The SSS Tab 4.2.7. The EEPROM Tab
5. Development Kit Hardware and Configuration x
5.1. Configuring FPGA Device and Accessing HPS Debug Access Port by JTAG 5.2. Configuring FPGA Device by AS Modes (Default Mode) 5.3. Configuring FPGA Device by AvST Modes 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card 5.4.2. HPS NAND Daughter Card
6. Custom Projects for the Development Kit x
6.1. Adding SmartVID settings in Quartus® Prime QSF file 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit User Guide
A. Development Kit Components
B. AG 7 FPGA F-Series XCVR-SoC DK Developer Resources
C. Safety and Regulatory Compliance Information

A.3. Clocks

Table 9.  Default Clock Frequency
Schematic Signal Name Default Frequency
FPGA_GPIO_REFCLKp/n0 156.25M
REFCLK_GXEp/n0 156.25M
SI53311_CLKOUT1p/n 156.25M
REFCLK_GXPp/n0 100M
REFCLK_GXPp/n2 100M
PCIE_RC_REFCLKp/n 100M
FPGA_GPIO_REFCLKp/n1 125M
SODIMM_REFCLKp/n 100M
FPGA_OSC_CLK_1 125M
FPGA_GPIO_REFCLK 100M
DDR4_COMP_REFCLKp/n 100M
FPGA_SYSTEM_CLK 100M
REFCLK_GXEp/n2 153.6M
REFCLK_GXEp/n3 184.32M
Cleaner_SYSTEM_P/N 184.32M
referenceclk_2 184.32M
referenceclk_3 153.6M

The LMK05028 device is a high-performance clock generator, jitter cleaner, and clock synchronizer with advanced reference clock selection and hitless switching to meet the stringent requirements of communications infrastructure applications. This clock device has two independent PLL cores, each can synchronize or lock to one of four reference clock inputs. It can generate up to eight output clocks with up to six different frequencies.

Two E-Tile transceiver recovery clocks (Cleaner_RECOVERY_p/n [0:1]) feed two of four reference clock inputs, single-end and differential SMA clocks feed other two inputs. LMK05028’s output clocks feed back to E-Tile transceiver bank, general I/O banks, and SMA connectors. You can set LMK05028 to power down mode through SW4.4.

Agilex™ 7 FPGA F-Series manages LMK05028 through general-purpose I/Os (Cleaner_GPIO[0:6], Cleaner_INSEL, Cleaner SCL/SDA, and Cleaner_status[0:1]). The connection between these general-purpose I/Os and FPGA can be shut down by SW10.2.

Figure 33. FPGA Clocks
Figure 34. Transceiver Clocks
Level Two Title