Intel® Agilex™ F-Series Transceiver-SoC Development Kit User Guide

ID 683752
Date 9/30/2022
Public
Document Table of Contents

A.3. Clocks

Table 10.  Default Clock Frequency
Schematic Signal Name Default Frequency
FPGA_GPIO_REFCLKp/n0 156.25M
REFCLK_GXEp/n0 156.25M
SI53311_CLKOUT1p/n 156.25M
REFCLK_GXPp/n0 100M
REFCLK_GXPp/n2 100M
PCIE_RC_REFCLKp/n 100M
FPGA_GPIO_REFCLKp/n1 125M
SODIMM_REFCLKp/n 100M
FPGA_OSC_CLK_1 125M
FPGA_GPIO_REFCLK 100M
DDR4_COMP_REFCLKp/n 100M
FPGA_SYSTEM_CLK 100M
REFCLK_GXEp/n2 153.6M
REFCLK_GXEp/n3 184.32M
Cleaner_SYSTEM_P/N 184.32M
referenceclk_2 184.32M
referenceclk_3 153.6M

The LMK05028 device is a high-performance clock generator, jitter cleaner and clock synchronizer with advanced reference clock selection and hitless switching to meet the stringent requirements of communications infrastructure applications. This clock device has two independent PLL cores that can each synchronize or lock to one of four reference clock inputs, and it can generate up to eight output clocks with up to six different frequencies.

Two E-tile transceiver recovery clocks (Cleaner_RECOVERY_p/n [0:1]) feed two of four reference clock inputs, single-end and differential SMA clocks feed other two inputs. LMK05028’s output clocks feed back to E-tile transceiver bank, general I/O banks and SMA connectors. LMK05028 can be set to power down mode by SW4.4.

Intel® Agilex™ F-Series FPGA manages LMK05028 through general purpose I/Os (Cleaner_GPIO[0:6], Cleaner_INSEL, Cleaner SCL/SDA, Cleaner_status[0:1]). The connection between these general purpose IOs and FPGA can be shut down by SW10.2.

Figure 19. FPGA Clocks
Figure 20. Transceiver Clocks

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