Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit User Guide

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ID 683752
Date 11/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit User Guide A. Development Kit Components B. AG 7 FPGA F-Series XCVR-SoC DK Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Altera® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board System MAX® 10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. Test the Functionality of the Development Kits 4.3. Control Onboard Clock through Clock Controller GUI 4.4. Control Onboard Power Regulator through Power Monitor GUI
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. Test the Functionality of the Development Kits x
4.2.1. The Configure Menu 4.2.2. The Sys Info Tab 4.2.3. The GPIO Tab 4.2.4. The XCVR Tab 4.2.5. The DDR4 Tab 4.2.6. The SSS Tab 4.2.7. The EEPROM Tab
5. Development Kit Hardware and Configuration x
5.1. Configuring FPGA Device and Accessing HPS Debug Access Port by JTAG 5.2. Configuring FPGA Device by AS Modes (Default Mode) 5.3. Configuring FPGA Device by AvST Modes 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card 5.4.2. HPS NAND Daughter Card
6. Custom Projects for the Development Kit x
6.1. Adding SmartVID settings in Quartus® Prime QSF file 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit User Guide
A. Development Kit Components
B. AG 7 FPGA F-Series XCVR-SoC DK Developer Resources
C. Safety and Regulatory Compliance Information

7. Document Revision History for the Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit User Guide

Document Version Changes
2025.11.07
  • Updated Recommended Operating Conditions in the Overview chapter.
  • Updated the Getting Started chapter:
    • Retitled topic Quartus® Prime Software and Driver Installation to Software and Driver Installation.
    • Removed the following topics:
    • Quick Start Guide
    • Design Examples
    • Added new topics:
      • Before you Begin
      • Handling the Board
      • Installing the Quartus® Prime Pro Edition Software
      • Installing the Altera® SoC EDS
      • Installing the Development Kit
      • Installing the Intel® FPGA Download Cable
  • Updated and retitled chapter topic Powering Up the Development Kit to Development Kit Setup:
    • Retitled topic Power Up to Powering Up the Development Kit.
    • Retitled topic Perform board restore to Performing Board Restore.
  • Updated the Board Test System chapter:
    • Retitled topic Installing the Quartus® Prime Software to Setting Up the Quartus® Prime Software for BTS Operation.
    • Retitled figures under Control Onboard Power Regulator through Power Monitor GUI for clarity.
    • Retitled the FPGA configuration topics under Development Kit and Hardware and Configuration for clarity.
  • Added new appendix chapter—Developer Resources.
  • Updated document for the latest branding standards.
  • Made editorial edits throughout the document.
2023.04.21
  • Added Figure: BTS GUI BTS GUI (for the Agilex™ 7 DK-SI-AGF014EA and DK-SI-AGF014E3ES Development KIts).
  • Added Figure: BTS GUI (for the Agilex™ 7 DK-SI-AGF014EB Development Kit).
  • Added Figure: QSFPDD - PLL and Pattern Status.
  • Added Figure: Power Monitor GUI - 1 (for the Agilex™ 7 DK-SI-AGF014EB Development Kit).
  • Added Figure: Power Monitor GUI - 2 (for the Agilex™ 7 DK-SI-AGF014EB Development Kit).
  • Added Figure: Power Monitor GUI - 3 (for the Agilex™ 7 DK-SI-AGF014EB Development Kit).
  • Added Figure: Power Monitor GUI - 4 (for the Agilex™ 7 DK-SI-AGF014EB Development Kit).
  • Added Figure: Power Tree (for the Agilex™ 7 DK-SI-AGF014EB Development Kit).
  • Added Figure: Power Sequence (for the Agilex™ 7 DK-SI-AGF014EB Development Kit).
  • Added Figure: I2C Serial Bus (for the Agilex™ 7 DK-SI-AGF014EB Development Kit).
  • Updated the Running the BTS GUI section.
  • Updated the The Sys Info Tab section.
  • Updated the The GPIO Tab section.
  • Updated the The DDR4 Tab section.
  • Updated the Control on-board power regulator through Power Monitor GUI section.
  • Updated the Add SmartVID settings in Quartus® Prime QSF file section.
  • Updated Table: Ordering Information.
  • Updated Figure: BTS Folder.
  • Updated Figure: Windows Console.
  • Updated Figure: Linux Console.
  • Updated Figure: The Configure Menu.
  • Updated Figure: The Sys Info Tab.
  • Updated Figure: The GPIO Tab.
  • Updated Figure: The XCVR Tab.
  • Updated Figure: QSFPDD - PMA Setting.
  • Updated Figure: QSFPDD - Data Rate.
  • Updated Figure: The DDR4 Tab.
  • Updated Figure: The SSS Tab.
  • Updated Figure: The EEPROM Tab.
  • Updated product family name to " Intel Agilex® 7".
  • Updated development kit name to Intel Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit.
  • Retitled the document from Intel® Agilex™ F-Series Transceiver-SoC Development Kit User Guide to Intel Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit User Guide.
2022.12.30
  • Added Section: Setting Up the BTS GUI Running Environment
  • Moved Control on-board clock through Clock Controller GUI and Control on-board power regulator through Power Monitor GUI to the Board Test System section.
2022.09.30 Updated the Additional Information section to include the UKCA declaration.
2022.06.21 Updated the Configure FPGA and access HPS Debug Access Port by JTAG section to provide more details on the TCK guidelines if attestation or Black Key Provisioning is enabled.
2021.07.27 Corrected Device Part Number for Intel® Agilex™ F-Series Transceiver-SoC Development Kit (Production) in Table: Ordering Information.
2021.06.15
  • Added Table: Ordering Information.
  • Updated Figure: Power Tree.
  • Removed SW9[1:2] switch from Table: Factory Default Switch Settings.
2021.03.17 Updated Control Onboard Clock through Clock Controller GUI
2020.07.09 Board Test System (BTS) information added
2020.05.01 Engineering Silicon (ES) Release
2019.09.30 Initial Release
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