Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit User Guide

Download PDF
ID 683752
Date 11/12/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit User Guide A. Development Kit Components B. AG 7 FPGA F-Series XCVR-SoC DK Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Altera® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board System MAX® 10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. Test the Functionality of the Development Kits 4.3. Control Onboard Clock through Clock Controller GUI 4.4. Control Onboard Power Regulator through Power Monitor GUI
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. Test the Functionality of the Development Kits x
4.2.1. The Configure Menu 4.2.2. The Sys Info Tab 4.2.3. The GPIO Tab 4.2.4. The XCVR Tab 4.2.5. The DDR4 Tab 4.2.6. The SSS Tab 4.2.7. The EEPROM Tab
5. Development Kit Hardware and Configuration x
5.1. Configuring FPGA Device and Accessing HPS Debug Access Port by JTAG 5.2. Configuring FPGA Device by AS Modes (Default Mode) 5.3. Configuring FPGA Device by AvST Modes 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card 5.4.2. HPS NAND Daughter Card
6. Custom Projects for the Development Kit x
6.1. Adding SmartVID settings in Quartus® Prime QSF file 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit User Guide
A. Development Kit Components
B. AG 7 FPGA F-Series XCVR-SoC DK Developer Resources
C. Safety and Regulatory Compliance Information

5.3. Configuring FPGA Device by AvST Modes

  1. Set SW1 to the AvST x32 mode first.
  2. Plug the SDM QSPI flash daughter into J11.
  3. The default system MAX® 10 image support AvST x32 mode only. You should build a corresponding .POF image if you select AvST x8 or AvST x16 configuration mode.
  4. Detect the QSPI flash in the Quartus® Prime Programmer and program the QSPI flash with the factory provided AvST x32 test image file. Power cycle the board, use the S17 push button to choose page, and S18 to configure FPGA. LED_D27, LED_28, LED_29 are used to indicate the active page.
    Table 6.  AvST x32 LED Behavior
    LED Page0 (XCVR) Page1 (DDR4) Page2 (SSS) Page3 (GPIO)
    LED_D27 ON OFF OFF OFF
    LED_D28 OFF ON OFF ON
    LED_D29 OFF OFF ON ON
    FPGA_LED_G[0] Blinking Blinking OFF/Blinking ON
    FPGA_LED_G[1] ON OFF OFF/Blinking ON
    FPGA_LED_G[2] ON ON OFF/Blinking ON
    FPGA_LED_G[3] ON OFF Blinking ON
    FPGA_LED_G[4] OFF OFF OFF ON
    FPGA_LED_G[5] OFF OFF OFF ON
    FPGA_LED_G[6] OFF OFF OFF ON
    FPGA_LED_G[7] OFF OFF OFF ON
Level Two Title