Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit User Guide

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ID 683752
Date 11/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit User Guide A. Development Kit Components B. AG 7 FPGA F-Series XCVR-SoC DK Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Altera® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board System MAX® 10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. Test the Functionality of the Development Kits 4.3. Control Onboard Clock through Clock Controller GUI 4.4. Control Onboard Power Regulator through Power Monitor GUI
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. Test the Functionality of the Development Kits x
4.2.1. The Configure Menu 4.2.2. The Sys Info Tab 4.2.3. The GPIO Tab 4.2.4. The XCVR Tab 4.2.5. The DDR4 Tab 4.2.6. The SSS Tab 4.2.7. The EEPROM Tab
5. Development Kit Hardware and Configuration x
5.1. Configuring FPGA Device and Accessing HPS Debug Access Port by JTAG 5.2. Configuring FPGA Device by AS Modes (Default Mode) 5.3. Configuring FPGA Device by AvST Modes 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card 5.4.2. HPS NAND Daughter Card
6. Custom Projects for the Development Kit x
6.1. Adding SmartVID settings in Quartus® Prime QSF file 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit User Guide
A. Development Kit Components
B. AG 7 FPGA F-Series XCVR-SoC DK Developer Resources
C. Safety and Regulatory Compliance Information

A.6. Communication Interfaces

PCIe* Slot

The PCIe* root port is a PCIe* 4.0 x16 port which fans out from Agilex™ 7 FPGA F-Series P-Tile. This port is designed to meet PCIe* 4.0 mother board requirement. The system MAX® 10 acts as the board management controller (BMC) of the development kit. It manages power up reset for both PCIe* root port (PCIE_RC_PERSTn) and PCIe* end point (PCIE_EP_PERSTn). In FPGA user mode, PCIe* root complex design can initiate PCIe* link reset through FPGA_GPIO[0] signals.

Table 13.   PCIe* Slot
Schematic Signal Name Description
PCIE_EP_PERSTn PCIe* endpoint reset
PCIE_RC_WAKEn PCIe* wake up
PCIE_RC_REFCLKp/n PCIe* reference clock
PCIE_RC_PRSNTn PCIe* present
I2C_PCIE_SCL/SDA PCIe* I2C bus
PCIE_RC_JTAG_TCK/TMS/TDO/TDI/TRSTn PCIe* JTAG bus
PCIE_RC_TXP/N[0:15] Transceiver TX
PCIE_RC_RXP/N[0:15] Transceiver RX

QSFP28

The QSFP28 port fans out from Agilex™ 7 FPGA F-Series E-Tile. All four channels can run up to 30G NRZ and 30G PAM4. Two of them can run up to 58G PAM4. This port supports 2x56G, 4x10G, and 4x25G application cases.

Table 14.  QSFP28
Schematic Signal Names Description
QSFP_MODPRSn Module present
QSFP_RESETn Module reset
QSFP_MODSELn Mode select
QSFP_INITMODE Initial mode
QSFP_INTn Interrupt
QSFP_I2C_SCL I2C clock
QSFP_I2C_SDA I2C data
ZQSFP_TXP/N[0:3] Transceiver TX
ZQSFP_RXP/N[0:3] Transceiver RX

QSFPDD

QSFPDD port fans out from Agilex™ 7 FPGA F-Series E-Tile. All eight channels can run up to 30G NRZ and 30G PAM4. Four of them can run up to 58G PAM4. This port is suitable for 2x56G, 4x10G, 4x25G and 8x25G application cases.

Table 15.  QSFPDD
Schematic Signal Names Description
QSFPDD_MODPRSn Module present
QSFPDD_RESETn Module reset
QSFPDD_MODSELn Mode select
QSFPDD_INITMODE Initial mode
QSFPDD_INTn Interrupt
QSFPDD_I2C_SCL I2C clock
QSFPDD_I2C_SDA I2C data
QSFPDD_TXP/N[0:7] Transceiver TX
QSFDDP_RXP/N[0:7] Transceiver RX

MXP

The MXP port fans out from Agilex™ 7 FPGA F-Series E-Tile. All four channels can run up to 30G NRZ and 30G PAM4. Two of them can run up to 58G PAM4. This port supports SMA to equipment, backplane, and different host compliance boards for 1x10G, 1x25G, 1x56G, 2x56G, 4x10G, and 4x25G cases.

Table 16.  MXP
Schematic Signal Names Description
MXP_TXP/N[0:3] Transceiver TX
MXP_RXP/N[0:3] Transceiver RX

10/100/1000M Triple-Speed Ethernet

The Triple-Speed Ethernet (TSE) port uses SGMII between 80E1111 PHY and Agilex™ 7 FPGA F-Series LVDS I/Os.

Table 17.  10/100/1000M Triple-Speed Ethernet
Schematic Signal Names Description
ETH_RSTn PHY reset
ETH_INTn Interrupt
ETH_MDC MDIO clock
ETH_MDIO MDIO data
ETH_SGMII_TXp/n SGMII TX
ETH_SGMII_RXp/n SGMII RX

Serial Buses

The SDM I/Os (SDM_IO0/12) and MAX® 10 I/Os (SDM_I2C_SCL/SDA) share the same I2C bus which talks with Agilex™ 7 FPGA core regulators. By default, SDM acts as SmartVID master and system MAX® 10 act as Power GUI master in this chain.

The system MAX® 10 I/Os (SYSMAX_I2C_SCL/SDA) manages the second I2C bus which access all I2C slaves except Agilex™ 7 FPGA core regulators. The slaves include power regulators, temperature monitor, voltage monitor, EEPROM, RTC, oscillator and PLLs.

The HPS I/Os (HPS_GPIO30/31) can access these two I2C chains by rework optional resistors.

Agilex™ 7 FPGA general I/Os (F2M_I2C_SCL/SDA) talks with system MAX® 10 and it cannot direct access these two I2C chains.

The Agilex™ 7 FPGA also manages Ethernet PHY, QSFP28, QSFPDD, SODIMM I2C buses, and LMK05028 SPI bus by GPIOs.

Table 18.  I2C Debug Headers
Schematic Signal Name Description
ENPIRION_I2C_SCL/SDA Enpirion* I2C header J35
SYSMAX_I2C_SCL/SDA System MAX® 10 I2C bus header J51
Cleaner_SCL/SDA Debug header for clock cleaner J26
Figure 35. I2C Serial Bus for Power Solution 2 Board (DK-SI-AGF014EB)
Figure 36. I2C Serial Bus for Power Solution 1 Board (DK-SI-AGF014EA and DK-SI-AGF014E3ES)
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