Intel® Agilex™ F-Series Transceiver-SoC Development Kit User Guide

ID 683752
Date 9/30/2022
Public
Document Table of Contents

A.4. General Input/Output

Table 11.  Intel Agilex FPGA
Schematic Signal Name Description
FPGA_LED_G [0:7] USER_LED[0:7]
FPGA_PB [0:7] USER_PB[0:7]
FPGA_SW [0:7] USER_DPSW[0:7]
FPGA_TESTIO [0:9] USER_IO[0:9]
FPGA_TEST_SCL/SDA/ALERTn USER_SMBUS
Table 12.  System Intel® MAX® 10
Schematic Signal Name Description
SYSMAX_LED_G0 PGM_LED0 for AvST configuration
SYSMAX_LED_G1 PGM_LED1 for AvST configuration
SYSMAX_LED_G2 PGM_LED2 for AvST configuration
SYSMAX_LED_G3 MAX_LOAD for AvST configuration
SYSMAX_LED_G4 MAX_CONF_DONE for AvST configuration
SYSMAX_LED_Y0 MAX_ERROR for AvST configuration
SYSMAX_LED_Y1 OVERTEMP
SYSMAX_PB0 MAX_RESETn
SYSMAX_PB1 CPU_RESETn
SYSMAX_PB2 HPS_COLD_RESETn
SYSMAX_PB3 RESERVED
SYSMAX_PB4 PGM_SEL for AvST configuration
SYSMAX_PB5 PGM_CFG for AvST configuration
SYSMAX_SW0 FACTORY_LOADn
SYSMAX_SW1

CLKSEL_156M

ON: SI53311_CLKSEL = 0

OFF: SI53311_CLKSEL = 1

SYSMAX_SW[2:3] USER_DIPSW
SYSMAX_SW4

I2C_3.3V_BUS_DEBUG_MODEn

ON: i2c_3.3v_en = 0

OFF: i2c_3.3v_en = 1

SYSMAX_SW5

CLKCleaner_IO_DEBUG_MODEn

ON: clkcleaner_io_tsn = 0

OFF: clkcleaner_io_tsn = 1

Table 13.  UB2/PWR Intel® MAX® 10
Schematic Signal Name Description
PWRMAX_LED_G0 FPGA Power Good
PWRMAX_LED_G1 System MAX10 Power Good
PWRMAX_LED_R0 Power Error
PWRMAX_LED_R1 Over Temperature
PWRMAX_PB0 RESERVED
PWRMAX_SW0 RESERVED
PWRMAX_SW1

VCCFUSEWR_SDM_FPGA_2.4V_SETn

ON: 2.4V, OFF: 1.8V

PWRMAX_SW2

VCCLHPS_FPGA_0.9V_BYPASSn

ON: From VCC core, OFF: From U60

PWRMAX_SW3

LMK05028_PDn

ON: Power Down, OFF: Power ON

PWRMAX_SW4

STBY_MODE0n

ON: Power Debug Mode 0, OFF: Normal

PWRMAX_SW5

STBY_MODE1n

ON: Power Debug Mode 1, OFF: Normal

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