Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit User Guide

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ID 683752
Date 11/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit User Guide A. Development Kit Components B. AG 7 FPGA F-Series XCVR-SoC DK Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Altera® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board System MAX® 10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. Test the Functionality of the Development Kits 4.3. Control Onboard Clock through Clock Controller GUI 4.4. Control Onboard Power Regulator through Power Monitor GUI
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. Test the Functionality of the Development Kits x
4.2.1. The Configure Menu 4.2.2. The Sys Info Tab 4.2.3. The GPIO Tab 4.2.4. The XCVR Tab 4.2.5. The DDR4 Tab 4.2.6. The SSS Tab 4.2.7. The EEPROM Tab
5. Development Kit Hardware and Configuration x
5.1. Configuring FPGA Device and Accessing HPS Debug Access Port by JTAG 5.2. Configuring FPGA Device by AS Modes (Default Mode) 5.3. Configuring FPGA Device by AvST Modes 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card 5.4.2. HPS NAND Daughter Card
6. Custom Projects for the Development Kit x
6.1. Adding SmartVID settings in Quartus® Prime QSF file 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit User Guide
A. Development Kit Components
B. AG 7 FPGA F-Series XCVR-SoC DK Developer Resources
C. Safety and Regulatory Compliance Information

A.4. General Input/Output

Table 10.   Agilex™ 7 FPGA
Schematic Signal Name Description
FPGA_LED_G [0:7] USER_LED[0:7]
FPGA_PB [0:7] USER_PB[0:7]
FPGA_SW [0:7] USER_DPSW[0:7]
FPGA_TESTIO [0:9] USER_IO[0:9]
FPGA_TEST_SCL/SDA/ALERTn USER_SMBUS
Table 11.  System MAX® 10
Schematic Signal Name Description
SYSMAX_LED_G0 PGM_LED0 for AvST configuration
SYSMAX_LED_G1 PGM_LED1 for AvST configuration
SYSMAX_LED_G2 PGM_LED2 for AvST configuration
SYSMAX_LED_G3 MAX_LOAD for AvST configuration
SYSMAX_LED_G4 MAX_CONF_DONE for AvST configuration
SYSMAX_LED_Y0 MAX_ERROR for AvST configuration
SYSMAX_LED_Y1 OVERTEMP
SYSMAX_PB0 MAX_RESETn
SYSMAX_PB1 CPU_RESETn
SYSMAX_PB2 HPS_COLD_RESETn
SYSMAX_PB3 RESERVED
SYSMAX_PB4 PGM_SEL for AvST configuration
SYSMAX_PB5 PGM_CFG for AvST configuration
SYSMAX_SW0 FACTORY_LOADn
SYSMAX_SW1

CLKSEL_156M

ON: SI53311_CLKSEL = 0

OFF: SI53311_CLKSEL = 1
SYSMAX_SW[2:3] USER_DIPSW
SYSMAX_SW4

I2C_3.3V_BUS_DEBUG_MODEn

ON: i2c_3.3v_en = 0

OFF: i2c_3.3v_en = 1
SYSMAX_SW5

CLKCleaner_IO_DEBUG_MODEn

ON: clkcleaner_io_tsn = 0

OFF: clkcleaner_io_tsn = 1
Table 12.  UB2/PWR MAX® 10
Schematic Signal Name Description
PWRMAX_LED_G0 FPGA Power Good
PWRMAX_LED_G1 System MAX10 Power Good
PWRMAX_LED_R0 Power Error
PWRMAX_LED_R1 Over Temperature
PWRMAX_PB0 RESERVED
PWRMAX_SW0 RESERVED
PWRMAX_SW1

VCCFUSEWR_SDM_FPGA_2.4V_SETn

ON: 2.4V, OFF: 1.8V
PWRMAX_SW2

VCCLHPS_FPGA_0.9V_BYPASSn

ON: From VCC core, OFF: From U60
PWRMAX_SW3

LMK05028_PDn

ON: Power Down, OFF: Power ON
PWRMAX_SW4

STBY_MODE0n

ON: Power Debug Mode 0, OFF: Normal
PWRMAX_SW5

STBY_MODE1n

ON: Power Debug Mode 1, OFF: Normal
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