External Memory Interfaces Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 4/01/2024
Document Table of Contents LPDDR3 Clock Signal

CK and CKn are differential clock inputs to the LPDDR3 interface. All the double data rate (DDR) inputs are sampled on both the positive and negative edges of the clock. Single data rate (SDR) inputs, CSn and CKE, are sampled at the positive clock edge.

The clock is defined as the differential pair which consists of CK and CKn. The positive clock edge is defined by the cross point of a rising CK and a falling CKn. The negative clock edge is defined by the cross point of a falling CK and a rising CKn.

The SDRAM data sheet specifies timing data for the following:

  • tDSH is the DQS falling edge hold time from CK.
  • tDSS is the DQS falling edge to the CK setup time.
  • tDQSS is the Write command to the first DQS latching transition.
  • tDQSCK is the DQS output access time from CK/CKn.