External Memory Interfaces Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 4/01/2024
Document Table of Contents

7.1.3. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: Mem I/O

Table 127.  Group: Mem I/O / Memory I/O Settings
Display Name Description
Output drive strength setting Specifies the output driver impedance setting at the memory device. (Identifier: MEM_LPDDR3_DRV_STR)
DQ ODT The ODT setting for the DQ pins during writes. (Identifier: MEM_LPDDR3_DQODT)
Power down ODT Turn on turn off ODT during power down. (Identifier: MEM_LPDDR3_PDODT)
Table 128.  Group: Mem I/O / ODT Activation
Display Name Description
Use Default ODT Assertion Tables Enables the default ODT assertion pattern as determined from vendor guidelines. These settings are provided as a default only; you should simulate your memory interface to determine the optimal ODT settings and assertion patterns. (Identifier: MEM_LPDDR3_USE_DEFAULT_ODT)