External Memory Interfaces Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 4/01/2024
Document Table of Contents

7.1.2. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: Memory

Table 125.  Group: Memory / Topology
Display Name Description
DQ width Total number of DQ pins in the interface. (Identifier: MEM_LPDDR3_DQ_WIDTH)
Number of clocks Number of CK/CK# clock pairs exposed by the memory interface. (Identifier: MEM_LPDDR3_CK_WIDTH)
Number of chip selects Total number of chip selects in the interface. (Identifier: MEM_LPDDR3_DISCRETE_CS_WIDTH)
Row address width The number of row address bits. (Identifier: MEM_LPDDR3_ROW_ADDR_WIDTH)
Column address width The number of column address bits. (Identifier: MEM_LPDDR3_COL_ADDR_WIDTH)
Bank address width The number of bank address bits. (Identifier: MEM_LPDDR3_BANK_ADDR_WIDTH)
Enable DM pins Indicates whether interface uses data mask (DM) pins. This feature allows specified portions of the data bus to be written to memory (not available in x4 mode). One DM pin exists per DQS group. (Identifier: MEM_LPDDR3_DM_EN)
Table 126.  Group: Memory / Latency and Burst
Display Name Description
Data latency Determines the mode register setting that controls the data latency. Sets both READ and WRITE latency (RL and WL). (Identifier: MEM_LPDDR3_DATA_LATENCY)
Burst length Burst length of the memory device. (Identifier: MEM_LPDDR3_BL)