External Memory Interfaces Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 11/28/2024
Public
Document Table of Contents

4.1.2.10. afi_reset_n for LPDDR3

AFI reset interface

Table 51.  Interface: afi_reset_nInterface type: Reset Output
Port Name Direction Description
afi_reset_n Output Reset for the AFI clock domain. Asynchronous assertion and synchronous deassertion