External Memory Interfaces Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 4/01/2024
Document Table of Contents General Guidelines

You should follow the recommended guidelines when performing pin placement for all external memory interface pins targeting Cyclone® 10 devices, whether you are using the hard memory controller or your own solution.

If you are using the hard memory controller, you should employ the relative pin locations defined in the <variation_name>/altera_emif_arch_nf_version number/<synth|sim>/<variation_name>_altera_emif_arch_nf_version number_<unique ID>_readme.txt file, which is generated with your IP.

Observe the following general guidelines when placing pins for your Cyclone® 10 external memory interface:

  1. Ensure that the pins of a single external memory interface reside within a single I/O column.
  2. An external memory interface can occupy one or more banks in the same I/O column. When an interface must occupy multiple banks, ensure that those banks are adjacent to one another.
  3. Any pin in the same bank that is not used by an external memory interface is available for use as a general purpose I/O of compatible voltage and termination settings.
  4. All address and command pins and their associated clock pins (CK and CK#) must reside within a single bank. The bank containing the address and command pins is identified as the address and command bank.
  5. To minimize latency, when the interface uses more than two banks, you must select the center bank of the interface as the address and command bank.
  6. The address and command pins and their associated clock pins in the address and command bank must follow a fixed pin-out scheme, as defined in the Cyclone® 10 External Memory Interface Pin Information File, which is available on www.altera.com.

    You do not have to place every address and command pin manually. If you assign the location for one address and command pin, the Fitter automatically places the remaining address and command pins.

    Note: The pin-out scheme is a hardware requirement that you must follow, and can vary according to the topology of the memory device. Some schemes require three lanes to implement address and command pins, while others require four lanes. To determine which scheme to follow, refer to the messages window during parameterization of your IP, or to the <variation_name>/altera_emif_arch_nf_<version>/<synth|sim>/<variation_name>_altera_emif_arch_nf_<version>_<unique ID>_readme.txt file after you have generated your IP.
  7. An unused I/O lane in the address and command bank can serve to implement a data group, such as a x8 DQS group. The data group must be from the same controller as the address and command signals.
  8. An I/O lane must not be used by both address and command pins and data pins.
  9. Place read data groups according to the DQS grouping in the pin table and Pin Planner. Read data strobes (such as DQS and DQS#) or read clocks (such as CQ and CQ# / QK and QK#) must reside at physical pins capable of functioning as DQS/CQ and DQSn/CQn for a specific read data group size. You must place the associated read data pins (such as DQ and Q), within the same group.
  10. You can implement two x4 DQS groups with a single I/O lane. The pin table specifies which pins within an I/O lane can be used for the two pairs of DQS and DQS# signals. In addition, for x4 DQS groups you must observe the following rules:
    • There must be an even number of x4 groups in an external memory interface.
    • DQS group 0 and DQS group 1 must be placed in the same I/O lane. Similarly, DQS group 2 and group 3 must be in the same I/O lane. Generally, DQS group X and DQS group X+1 must be in the same I/O lane, where X is an even number.
    • When placing DQ pins in x4 mode, it is important to stay within an I/O lane when swapping pin locations. In other words, you may swap DQ pins within a given DQS group or across an adjacent DQS group, so long as you are within the same I/O lane. The following table illustrates an example, where DATA_A and DATA_B are swap groups, meaning that any pin in that index can move within that range of pins.
      Index Within Lane DQS x4 Locations
      11 DATA_B[3:0]
      10 DATA_B[3:0]
      9 DQS_Bn
      8 DQS_Bp
      7 DATA_B[3:0]
      6 DATA_B[3:0]
      5 DQS_An
      4 DQS_Ap
      3 DATA_A[3:0]
      2 DATA_A[3:0]
      1 DATA_A[3:0]
      0 DATA_A[3:0]
  11. You should place the write data groups according to the DQS grouping in the pin table and Pin Planner.
  12. For protocols and topologies with bidirectional data pins where a write data group consists of multiple read data groups, you should place the data groups and their respective write and read clock in the same bank to improve I/O timing.

    You do not need to specify the location of every data pin manually. If you assign the location for the read capture strobe/clock pin pairs, the Fitter will automatically place the remaining data pins.

  13. Ensure that DM/BWS pins are paired with a write data pin by placing one in an I/O pin and another in the pairing pin for that I/O pin. It is recommended—though not required—that you follow the same rule for DBI pins, so that at a later date you have the freedom to repurpose the pin as DM.

Multiple Interfaces in the Same I/O Column

To place multiple interfaces in the same I/O column, you must ensure that the global reset signals (global_reset_n) for each individual interface all come from the same input pin or signal.

I/O Banks Selection

  • For each memory interface, select adjacent I/O banks. To determine whether I/O banks are adjacent, refer to the I/O Pin Counts tables located in the Cyclone® 10 Core Fabric and General Purpose I/Os Handbook. You can always assume I/O banks are adjacent within an I/O column except in the following conditions:
    • When an I/O bank is not bonded out on the package (contains the '-' symbol in the I/O table).
    • An I/O bank does not contain 48 pins, indicating that it is only partially bonded out.
  • A memory interface can only span across I/O banks in the same I/O column.
  • Because I/O bank 2A is also employed for configuration-related operations, you can use it to construct external memory interfaces only when the following conditions are met:
    • The pins required for configuration related use (such as configuration bus for Fast Passive Parallel mode or control signals for Partial Reconfiguration) are never shared with pins selected for EMIF use, even after configuration is complete.
    • The I/O voltages are compatible.
    • The design has achieved a successful fit in the Quartus® Prime software.

    Refer to the Cyclone® 10 Device Handbook and the Configuration Function column of the Pin-Out files for more information about pins and configuration modes.

  • The number of I/O banks that you require depends on the memory interface width.
  • A memory interface using I/O banks 2K and 2L (3V I/O bank) with the configuration described below, may fit successfully without the lower frequency restriction caused by not using OCT:
    • Place address/command in I/O bank 2L and configure the IP FPGA I/O tab address/command and memory clock to have current strength outputs.
    • Place DQS groups in I/O bank 2K and configure the IP FPGA I/O tab data bus to use input and output terminations with calibrated OCT.
    • Place the RZQ pin in I/O bank 2K.
    • For a single-ended clock, place the PLL reference clock on a spare dedicated input clock pin in I/O bank 2K or 2L. For an LVDS clock, if the DQS groups do not use all the I/O lanes in I/O bank 2K and there is a spare differential clock input, place the PLL reference clock there.
    • Verify that the design fits successfully and closes timing.
  • In some device packages, the number of I/O pins in some LVDS I/O banks is less than 48 pins.

Address/Command Pins Location

  • All address/command pins for a controller must be in a single I/O bank.
  • If your interface uses multiple I/O banks, the address/command pins must use the middle bank. If the number of banks used by the interface is even, any of the two middle I/O banks can be used for address/command pins.
  • Address/command pins and data pins cannot share an I/O lane but can share an I/O bank.
  • The address/command pin locations for the soft and hard memory controllers are predefined. In the External Memory Interface Pin Information for Devices spreadsheet, each index in the "Index within I/O bank" column denotes a dedicated address/command pin function for a given protocol. The index number of the pin specifies to which I/O lane the pin belongs:
    • I/O lane 0—Pins with index 0 to 11
    • I/O lane 1—Pins with index 12 to 23
    • I/O lane 2—Pins with index 24 to 35
    • I/O lane 3—Pins with index 36 to 47
  • For memory topologies and protocols that require only three I/O lanes for the address/command pins, use I/O lanes 0, 1, and 2.
  • Unused address/command pins in an I/O lane can be used as general-purpose I/O pins.

CK Pins Assignment

Assign the clock pin (CK pin) according to the number of I/O banks in an interface:

  • If the number of I/O banks is odd, assign one CK pin to the middle I/O bank.
  • If the number of I/O banks is even, assign the CK pin to either of the middle two I/O banks.

Although the Fitter can automatically select the required I/O banks, Intel® recommends that you make the selection manually to reduce the pre-fit run time.

PLL Reference Clock Pin Placement

Place the PLL reference clock pin in the address/command bank. Other I/O banks may not have free pins that you can use as the PLL reference clock pin:

  • If you are sharing the PLL reference clock pin between several interfaces, the I/O banks must be consecutive.

The Cyclone® 10 external memory interface IP does not support PLL cascading.

RZQ Pin Placement

You may place the RZQ pin in any I/O bank in an I/O column with the correct VCCIO and VCCPT for the memory interface I/O standard in use. However, the recommended location is in the address/command I/O bank, for greater flexibility during debug if a narrower interface project is required for testing.

DQ and DQS Pins Assignment

Intel® recommends that you assign the DQS pins to the remaining I/O lanes in the I/O banks as required:

  • Constrain the DQ and DQS signals of the same DQS group to the same I/O lane.
  • You cannot constrain DQ signals from two different DQS groups to the same I/O lane.

If you do not specify the DQS pins assignment, the Fitter selects the DQS pins automatically.

Sharing an I/O Bank Across Multiple Interfaces

If you are sharing an I/O bank across multiple external memory interfaces, follow these guidelines:

  • The interfaces must use the same protocol, voltage, data rate, frequency, and PLL reference clock.
  • You cannot use an I/O bank as the address/command bank for more than one interface. The memory controller and sequencer cannot be shared.
  • You cannot share an I/O lane. There is only one DQS input per I/O lane, and an I/O lane can connect to only one memory controller.