External Memory Interfaces Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 4/01/2024
Document Table of Contents Implementing a x8 Interface with Hard Memory Controller

The following diagram illustrates the use of a single I/O bank to implement a DDR3 x8 interface using the hard memory controller.
Figure 4. Single Bank x8 Interface With Hard Controller

In the above diagram, shaded cells indicate resources that are in use.

Note: For information on the I/O lanes and pins in use, consult the pin table for your device or the readme.txt file generated with your IP.