External Memory Interfaces Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 11/28/2024
Public
Document Table of Contents

4.1.1.17. emif_usr_clk_sec for DDR3

User clock interface (for the secondary interface in ping-pong configuration)

Table 25.  Interface: emif_usr_clk_secInterface type: Clock Output
Port Name Direction Description
emif_usr_clk_sec Output User clock domain. Intended for the secondary interface in a ping-pong configuration.