External Memory Interfaces Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 4/01/2024
Document Table of Contents I/O Timing

I/O timing analysis includes analysis of read capture, write, address and command, DQS gating, and write leveling.

The Timing Analyzer provides a breakdown of the timing budgets which details margin loss due to transmitter, receiver, and channel. The Timing Analyzer displays the total margin in the last row of the timing report.

The I/O timing analysis described in the following topics is based on a 5 speed-grade device, interfacing with a DDR3 SDRAM UDIMM at 933 MHz. A 933 MHz DDR3 SDRAM UDIMM is used for the analysis.