External Memory Interfaces Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 4/01/2024
Document Table of Contents

9.4.3. Calibration

The time needed for calibration varies, depending on many factors including the interface width, the number of ranks, frequency, board layout, and difficulty of calibration.

The following table lists approximate typical calibration times for various protocols and configurations.

Table 158.   Cyclone® 10 EMIF IP Approximate Calibration Times
Protocol Rank and Frequency Typical Calibration Time
DDR3, x64 UDIMM, DQS x8, DM on 1 rank, 933 MHz 102 ms
1 rank, 800 MHz 106 ms
2 rank, 933 MHz 198 ms
2 rank, 800 MHz 206 ms