External Memory Interfaces Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 4/01/2024
Document Table of Contents

3.1. EMIF Architecture: Introduction

The Cyclone® 10 GX architecture contains many hardware features designed to meet the high-speed requirements of emerging memory protocols, while consuming the smallest amount of core logic area and power.

The following are key hardware features of the architecture:

Hard Sequencer

The sequencer employs a hardened processor, and can perform memory calibration for a wide range of protocols. You can share the sequencer among multiple memory interfaces of the same or different protocols.

Hard PHY

The hard PHY can interface with external memories running at speeds of up to 1.2 GHz. The PHY circuitry is hardened in the silicon, which simplifies the challenges of achieving timing closure and minimal power consumption.

Hard Memory Controller

The hard memory controller reduces latency and minimizes core logic consumption in the external memory interface. The hard memory controller supports the DDR3 and LPDDR3 memory protocols.

PHY-Only Mode

The EMIF IP provides a PHY-only option, which allows you to use your own custom soft controller. When selected, the PHY-only option generates only the PHY and sequencer, but not the controller, thus providing a mechanism by which you can integrate your own custom soft controller.

High-Speed PHY Clock Tree

Dedicated high speed PHY clock networks clock the I/O buffers. The PHY clock trees exhibit low jitter and low duty cycle distortion, maximizing the data valid window.

Automatic Clock Phase Alignment

Automatic clock phase alignment circuitry dynamically adjusts the clock phase of core clock networks to match the clock phase of the PHY clock networks. The clock phase alignment circuitry minimizes clock skew that can complicate timing closure in transfers between the FPGA core and the periphery.

Resource Sharing

The device architecture simplifies resource sharing between memory interfaces. Resources such as the OCT calibration block, PLL reference clock pin, and core clock can be shared. The hard Nios processor in the I/O AUX is shared across all interfaces in a column.