Differences Among Intel SoC Device Families

ID 683648
Date 8/22/2018

HPS System Memory Management Differences

System Memory Management Feature Cyclone V SoC Arria V SoC Arria 10 SoC Stratix 10 SoC
SMMU implementation None None None ARM MMU-500 r2p0

The Stratix 10 HPS includes a system memory management unit (SMMU) which is responsible for translating virtual addresses to physical addresses. Distributed translation buffer units (TBUs), located between system masters and the L3 interconnect, communicate with the central translation control unit (TCU). The TBUs for the following components accelerate mapping by caching translations:

  • USB
  • Ethernet media access controller (EMAC)
  • NAND controller
  • SD/MMC
  • Embedded trace router (ETR)
  • DMA
  • FPGA-to-HPS bridge

The SMMU allows drivers executing in the MPU to pass virtual addresses directly to peripherals that master memory. This capability reduces driver overhead and complexity, compared to performing virtual-to-physical address translation in software.