HPS Cache Coherency Controller Differences
|Cache Coherency Controller Feature||Cyclone V SoC||Arria V SoC||Arria 10 SoC||Stratix 10 SoC|
|System level cache coherency||Implemented by ACP in MPCore and ACP ID mapper block||Implemented by ACP in MPCore and ACP ID mapper block||Implemented by ACP in MPCore and level 3 (L3) interconnect||Implemented by cache coherency unit (CCU)|
Cyclone V, Arria V, and Arria10 SoC devices implement system level cache coherency by exposing the MPU accelerator coherency port (ACP) to masters in the system including the FPGA fabric connected to the FPGA-to-HPS bridge. The Cyclone V and Arria V SoCs require these masters to access the ACP ID mapper while Arria 10 SoC only requires the masters to perform cacheable accesses to the MPU cache subsystem.
The Stratix 10 HPS includes a cache coherency unit that resides between the MPU and the rest of the system, allowing cacheable accesses from masters in the system, including soft IP in the FPGA fabric connected to the FPGA-to-HPS bridge. The Stratix 10 HPS CCU also performs routing functionality between the MPU, FPGA-to-HPS bridge, L3 interconnect, and SDRAM scheduler.
Did you find the information on this page useful?