HPS SDRAM Controller Subsystem Differences
| SDRAM Controller Subsystem Features | Cyclone V SoC | Arria V SoC | Arria 10 SoC | Stratix 10 SoC |
|---|---|---|---|---|
| HPS SDRAM bandwidth | 8, 16, or 32 bits, up to 400 MHz | 8, 16, or 32 bits, up to 533 MHz | 16, 32, or 64 bits, up to 1200 MHz | 16, 32, or 64 bits, up to 1066 MHz |
| Supported SDRAM standards | Double data rate 3 (DDR3) DDR2 Low power DDR2 (LPDDR2) |
DDR3 DDR2 LPDDR2 |
DDR4 DDR3 |
DDR4 DDR3 |
| FPGA-to-SDRAM available port sizes | 32 bits 64 bits 128 bits |
32 bits 64 bits 128 bits |
32 bits 64 bits 128 bits |
32 bits 64 bits 128 bits |
| FPGA-to-SDRAM maximum total interface width | 256 bits | 256 bits | 256 bits | 384 bits |
| Controller implementation | Dedicated controller in the HPS | Dedicated controller in the HPS | Uses the hard memory controller (HMC) in the FPGA I/O column, bank 2K | Uses the HMC in the FPGA I/O column, bank 2M |
| External SDRAM interface I/O pin locations | Fixed locations in the HPS I/O | Fixed locations in the HPS I/O | Uses DDR I/O in the FPGA I/O column See table below for bank assignments |
Uses DDR I/O in the FPGA I/O column See table below for bank assignments |
| Shared access management | Multi port front end (MPFE) in the HPS SDRAM controller subsystem | MPFE in the HPS SDRAM controller subsystem | Arteris FlexNoC scheduler in the HPS SDRAM L3 Interconnect | Arteris FlexNoC scheduler in the HPS SDRAM L3 Interconnect |
| Device and package support for x64/72 external SDRAM interfaces (64 data bits, 8 ECC bits) | N/A | N/A | KF40 package only | All device and package combinations |
| Supports HPS and core external memory interface (EMIF) instances in the same I/O column | N/A | N/A | No | Yes |
| Mem I/O | Bank | |
|---|---|---|
| Arria 10 SoC | Stratix 10 Soc | |
| Data[63:32] | 2I | 2L |
| Data[31:0] | 2J | 2N |
| Address, Command and ECC | 2K | 2M |