HPS SDRAM Controller Subsystem Differences
| SDRAM Controller Subsystem Feature | Cyclone® V SoC, Arria® V SoC |
Arria® 10 SoC | Stratix® 10 SoC | Agilex™ 7 F-Series/I-Series/ M-Series SoC |
Agilex™ 5 E-Series/D-Series SoC |
Agilex™ 3 C-Series SoC |
|---|---|---|---|---|---|---|
| HPS SDRAM bandwidth | 8, 16, or 32 bits, up to 400 MHz | 16, 32, or 64 bits, up to 1200 MHz | 16, 32, or 64 bits, up to 1066 MHz | F/I-Series: 16, 32, or 64-bits, up to 1600 MHz M-Series: 16 or 32 bits, up to 2800 MHz |
16 or 32 bits Refer to the Agilex™ 5 FPGAs and SoCs Device Data Sheet for device speed grades. |
16 or 32 bits Refer to the Agilex™ 3 FPGAs and SoCs Device Data Sheet for device speed grades. |
| Supported SDRAM standards | Double data rate 3 (DDR3) DDR2 Low power DDR2 (LPDDR2) |
DDR4 DDR3 |
DDR4 DDR3 |
F/I-Series: DDR4 (x64/72) M-Series: DDR4 (x32+ECC) DDR5 (x32+ECC) LPDDR5 (1x32, 2x16) |
D-Series: DDR4 (x32+ECC) DDR5 (x32+ECC) LPDDR4 (1x32, 2x16) LPDDR5 (1x32, 2x16) E-Series: Group A: DDR4 (x32+ECC) DDR5 (x32+ECC) LPDDR4 (1x32, 2x16) LPDDR5 (1x32, 2x16) Group B: DDR4 (x32+ECC) LPDDR4 (1x32, 2x16) LPDDR5 (1x32, 2x16) |
LPDDR4 (1x32, 2x16) |
FPGA-to-HPS |
32 bits 64 bits 128 bits |
128 bits |
128 bits |
Single Port: F/I-Series 128, 256, 512 bits Single Port: M-Series 128, 256 bits |
256 bits |
256 bits |
| FPGA-to-SDRAM available port sizes | 32 bits 64 bits 128 bits |
32 bits 64 bits 128 bits |
32 bits 64 bits 128 bits |
64 bits 128 bits 256 bits |
64 bits 128 bits 256 bits |
|
| FPGA-to-SDRAM maximum total interface width | 256 bits | 256 bits | 384 bits | 512 bits |
256 bits |
256 bits |
| Controller implementation | Dedicated controller in the HPS | Uses the hard memory controller (HMC) in the FPGA I/O column, bank 2I, 2J and 2K | Uses the HMC in the FPGA I/O column, bank 2L, 2M and 2N | Uses the HMC in the FPGA I/O column, bank 3C, 3D |
Uses the HMC in the FPGA I/O column, bank 3A, 3B |
Uses the HMC in the FPGA I/O column, bank 3A |
| External SDRAM interface I/O pin locations | Fixed locations in the HPS I/O | Uses DDR I/O in the FPGA I/O column, bank 2I, 2J and 2K |
Uses DDR I/O in the FPGA I/O column, bank 2L, 2M and 2N |
Uses DDR I/O in the FPGA I/O column, bank 3C and 3D |
Uses DDR I/O in the FPGA I/O column, bank 3A and 3B |
Uses DDR I/O in the FPGA I/O column, bank 3A |
| Shared access management | Multi port front end (MPFE) in the HPS SDRAM controller subsystem | Arteris FlexNoC scheduler in the HPS SDRAM L3 Interconnect | Arteris FlexNoC scheduler in the HPS SDRAM L3 Interconnect | Arteris FlexNoC scheduler in the HPS SDRAM L3 Interconnect |
Arteris FlexNoC scheduler in the HPS MPFE NOC (Version 4.x) |
Arteris FlexNoC scheduler in the HPS MPFE NOC (Version 4.x) |
| Device and package support for x64/72 external SDRAM interfaces (64 data bits, 8 ECC bits) | N/A | KF40 package only | All device and package combinations | All device and package combinations |
See above for supported SDRAM interfaces. |
See above for supported SDRAM interfaces. |
| Supports HPS and core external memory interface (EMIF) instances in the same I/O column | N/A | No | Yes | Yes |
Yes |
Yes |