Overview of HPS Modules
HPS Micro Processor Unit Subsystem Differences
Booting and Configuration Differences
Cache Coherency Unit Differences
Generic Interrupt Controller Differences
HPS System Memory Management Unit Differences
HPS On-Chip RAM Differences
HPS Error Correction Differences
HPS DMA Controller Differences
HPS Clock Manager Differences
HPS Reset Manager Differences
HPS FPGA Manager Differences
HPS System Manager Differences
HPS Scan Manager Differences
HPS Security Feature Differences
HPS System Interconnect and Firewalls Differences
HPS-FPGA Bridge Differences
HPS General Purpose I/O Interface Differences
I/O Pin Multiplexing Differences
HPS Mailbox Differences
HPS SDRAM Controller Subsystem Differences
HPS NAND Flash Controller Differences
HPS SD/eMMC Host Controller Differences
Combo DLL PHY Differences
HPS Quad SPI Flash Controller Differences
HPS USB 2.0 OTG Controller Differences
HPS USB 3.1 Gen1 Controller Differences
HPS EMAC Differences
HPS SPI Controller Differences
HPS I2C Controller Differences
I3C Controller Differences
HPS UART Controller Differences
HPS CAN Controller Differences
HPS Timer Differences
HPS Watchdog Timer Differences
HPS CoreSight Debug and Trace Differences
Revision History for Differences Among Altera® SoC Device Families
HPS CoreSight Debug and Trace Differences
| CoreSight Debug and Trace Feature | Cyclone® V SoC, Arria® V SoC |
Arria® 10 SoC | Stratix® 10 SoC, Agilex™ 7 F-Series/I-Series/ M-Series SoC |
Agilex™ 5 E-Series/D-Series SoC, Agilex™ 3 C-Series SoC |
|---|---|---|---|---|
| Coresight version | Coresight (Arm* DGI 0012D) | Coresight (Arm* DGI 0012D) | Coresight SoC-400 | Coresight SoC-400 |
| Trace width to HPS I/O | 8 bits | 4 bits | 16 bits | 16 bits |
| Trace width to FPGA I/O | 32 bits | 16 bits | 32 bits | 32 bits |
| MPU Embedded Trace FIFO | — | — | — | Added a 8 kB ETF in the MPU to capture trace packets from both the CPUs |
| Centralized Embedded Trace FIFO (ETF) Size | 32 kB | 32 kB | 32 kB | 32 kB |