Differences Among Altera® SoC Device Families

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ID 683648
Date 8/29/2025
Public
Document Table of Contents
Document Table of Contents x
Differences Among Altera® SoC Device Families
Differences Among Altera® SoC Device Families x
Overview of HPS Modules HPS Micro Processor Unit Subsystem Differences Booting and Configuration Differences Cache Coherency Unit Differences Generic Interrupt Controller Differences HPS System Memory Management Unit Differences HPS On-Chip RAM Differences HPS Error Correction Differences HPS DMA Controller Differences HPS Clock Manager Differences HPS Reset Manager Differences HPS FPGA Manager Differences HPS System Manager Differences HPS Scan Manager Differences HPS Security Feature Differences HPS System Interconnect and Firewalls Differences HPS-FPGA Bridge Differences HPS General Purpose I/O Interface Differences I/O Pin Multiplexing Differences HPS Mailbox Differences HPS SDRAM Controller Subsystem Differences HPS NAND Flash Controller Differences HPS SD/eMMC Host Controller Differences Combo DLL PHY Differences HPS Quad SPI Flash Controller Differences HPS USB 2.0 OTG Controller Differences HPS USB 3.1 Gen1 Controller Differences HPS EMAC Differences HPS SPI Controller Differences HPS I2C Controller Differences I3C Controller Differences HPS UART Controller Differences HPS CAN Controller Differences HPS Timer Differences HPS Watchdog Timer Differences HPS CoreSight Debug and Trace Differences Revision History for Differences Among Altera® SoC Device Families
Differences Among Altera® SoC Device Families

I/O Pin Multiplexing Differences

The available I/Os on SoC devices are divided into the following categories:

  • Dedicated function: Each I/O has only one function and cannot be used for other purposes.
  • Dedicated I/O with loaner capability: The I/Os are primarily used by the HPS, but individual I/Os can be used by the FPGA if the HPS is not using them.
  • Dedicated I/O: The I/Os can be used only by the HPS. The pins are not accessible to logic in the FPGA.
  • Shared I/O: The I/Os can be used by either the HPS or the FPGA. These pins are used by high-speed peripherals such as EMAC and USB.
  • FPGA I/O: These I/Os can only be used by the FPGA. Slow speed peripherals can be routed through the FPGA fabric and assigned to FPGA I/O.
HPS I/O Pin Multiplexing Feature

Cyclone® V SoC,

Arria® V SoC		 Arria® 10 SoC

Agilex™ 7

F-Series/I-Series/

M-Series SoC

Agilex™ 5

E-Series/D-Series SoC,

Agilex™ 3

C-Series SoC
Reset pins 3 dedicated functions 2 dedicated functions Choose one of the available SDM optional pins Choose one of the available SDM optional pins
Clock pins 2 dedicated functions 1 dedicated function Choose one of the 48 dedicated I/Os Choose one of the 48 dedicated I/Os
JTAG pins

5 dedicated pins

JTAG interface is independent of FPGA JTAG interfaces

 Chained internally into FPGA JTAG interface

4 optional pins from the 48 dedicated I/Os

Independent or chained internally into FPGA JTAG interface

4 optional pins from the 48 dedicated I/Os

Independent or chained internally into FPGA JTAG interface
Peripheral pins
  • Cyclone® V SoC: Up to 67 dedicated I/Os with loaner capability
  • Arria® V SoC: Up to 94 dedicated I/Os with loaner capability

14 dedicated I/Os 20

48 shared I/Os

48 dedicated I/Os (including pins used for clock and JTAG)

20

48 dedicated I/Os (including pins used for clock and JTAG)

20
Supported voltage

3.3V, 2.0V, 2.5V, 1.8V, 1.5V

3.0V, 2.5V, 1.8V

 1.8V 1.8V
20 Does not support loaner capability.
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