Differences Among Altera® SoC Device Families

Download PDF
ID 683648
Date 8/29/2025
Public
Document Table of Contents
Document Table of Contents x
Differences Among Altera® SoC Device Families
Differences Among Altera® SoC Device Families x
Overview of HPS Modules HPS Micro Processor Unit Subsystem Differences Booting and Configuration Differences Cache Coherency Unit Differences Generic Interrupt Controller Differences HPS System Memory Management Unit Differences HPS On-Chip RAM Differences HPS Error Correction Differences HPS DMA Controller Differences HPS Clock Manager Differences HPS Reset Manager Differences HPS FPGA Manager Differences HPS System Manager Differences HPS Scan Manager Differences HPS Security Feature Differences HPS System Interconnect and Firewalls Differences HPS-FPGA Bridge Differences HPS General Purpose I/O Interface Differences I/O Pin Multiplexing Differences HPS Mailbox Differences HPS SDRAM Controller Subsystem Differences HPS NAND Flash Controller Differences HPS SD/eMMC Host Controller Differences Combo DLL PHY Differences HPS Quad SPI Flash Controller Differences HPS USB 2.0 OTG Controller Differences HPS USB 3.1 Gen1 Controller Differences HPS EMAC Differences HPS SPI Controller Differences HPS I2C Controller Differences I3C Controller Differences HPS UART Controller Differences HPS CAN Controller Differences HPS Timer Differences HPS Watchdog Timer Differences HPS CoreSight Debug and Trace Differences Revision History for Differences Among Altera® SoC Device Families
Differences Among Altera® SoC Device Families

Overview of HPS Modules

Feature

Cyclone® V SoC,

Arria® V SoC

 Arria® 10 SoC

Stratix® 10 SoC,

Agilex™ 7 F-Series/I-Series/M-Series SoC

Agilex™ 5 E-Series/D-Series SoC,

Agilex™ 3 C-Series SoC
Micro Processor Unit (MPU) Single/Dual Cortex* -A9 Dual Cortex* -A9 Quad Cortex* -A53 Dual Cortex* -A76 and dual Cortex* -A55 with DSU 1
Cache Coherency Controller Accelerator coherency port (ACP) ACP Cache Coherency Unit (CCU) CCU
Generic Interrupt Controller (GIC) Yes Yes Yes Yes
System Memory Management Unit (SMMU) No No Yes Yes
On-Chip RAM (OCRAM) 64 KB 256 KB 256 KB 512 KB
Ethernet Media Access Controller (EMAC) 2 3 3 3
DMA Controller 1 1 1 2
NAND Flash Controller Yes Yes Yes Yes
SD/eMMC Host Controller Yes Yes Yes Yes
Combo DLL PHY No No No Yes
Quad SPI Flash Controller Yes (inside HPS) Yes (inside HPS) No (outside of HPS, uses SDM) No (outside of HPS, uses SDM)
USB 3.1 Gen 1 Controller No No No 1
USB 2.0 OTG Controller 2 2 2 1
I3C Controller No No No 2
I2C Controller 4 5 5 5
SPI Controller 2 masters and 2 slaves 2 masters and 2 slaves 2 masters and 2 slaves 2 masters and 2 slaves
Timers 4 4 4 4
Watchdog Timers 2 2 4 5
UART Controller 2 2 2 2
Controller Area Network (CAN) Controller 2 No No No
General-Purpose I/O Interface (GPIO) Yes Yes Yes Yes
Hard Processor System I/O Pin Multiplexing

Dedicated I/O with Loaner capability for Cyclone V SoC: 67

Dedicated I/O with Loaner capability for Arria V SoC: 94

Dedicated I/O: 17

Shared I/O: 48

Dedicated I/O: 48

Shared I/O: 0

Dedicated I/O: 48

Shared I/O: 0
System Manager Yes Yes Yes Yes
Clock Manager Yes Yes Yes Yes
Reset Manager Yes Yes Yes Yes
FPGA Manager Yes Yes No (uses SDM) No (uses SDM)
Scan Manager Yes No No No
Security Manager No Yes No (uses SDM) No (uses SDM)
HPS-FPGA Bridges Yes Yes Yes Yes
SDRAM Controller Inside HPS Outside of HPS Outside of HPS Outside of HPS
System Interconnect Yes Yes Yes Yes
Error Checking and Correction (ECC) Controller No Yes Yes Yes
CoreSight Debug and Trace Yes Yes Yes Yes
Secure Device Manager (SDM) Interface No No Yes Yes
Booting and Configuration

3 options:

HPS Boot and FPGA Configuration occur separately, FPGA Configuration First, HPS Boot First

3 options:

HPS Boot and FPGA Configuration occur separately, FPGA Configuration First, HPS Boot First

2 options:

FPGA Configuration First, HPS Boot First

2 options:

FPGA Configuration First, HPS Boot First
Refer to the respective chapters for detailed information of the differences across different families.
1 Agilex™ 3 SoC supports dual Cortex* -A55 only.
Level Two Title