Differences Among Altera® SoC Device Families

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ID 683648
Date 8/29/2025
Public
Document Table of Contents
Document Table of Contents x
Differences Among Altera® SoC Device Families
Differences Among Altera® SoC Device Families x
Overview of HPS Modules HPS Micro Processor Unit Subsystem Differences Booting and Configuration Differences Cache Coherency Unit Differences Generic Interrupt Controller Differences HPS System Memory Management Unit Differences HPS On-Chip RAM Differences HPS Error Correction Differences HPS DMA Controller Differences HPS Clock Manager Differences HPS Reset Manager Differences HPS FPGA Manager Differences HPS System Manager Differences HPS Scan Manager Differences HPS Security Feature Differences HPS System Interconnect and Firewalls Differences HPS-FPGA Bridge Differences HPS General Purpose I/O Interface Differences I/O Pin Multiplexing Differences HPS Mailbox Differences HPS SDRAM Controller Subsystem Differences HPS NAND Flash Controller Differences HPS SD/eMMC Host Controller Differences Combo DLL PHY Differences HPS Quad SPI Flash Controller Differences HPS USB 2.0 OTG Controller Differences HPS USB 3.1 Gen1 Controller Differences HPS EMAC Differences HPS SPI Controller Differences HPS I2C Controller Differences I3C Controller Differences HPS UART Controller Differences HPS CAN Controller Differences HPS Timer Differences HPS Watchdog Timer Differences HPS CoreSight Debug and Trace Differences Revision History for Differences Among Altera® SoC Device Families
Differences Among Altera® SoC Device Families

HPS EMAC Differences

EMAC Feature Cyclone® V SoC,

Arria® V SoC

 Arria® 10 SoC Stratix® 10 SoC,

Agilex™ 7

F-Series/I-Series/

M-Series SoC

Agilex™ 5

E-Series/D-Series SoC,

Agilex™ 3

C-Series SoC
Synopsys IP version GMAC 3.70a GMAC 3.72a GMAC 3.73a XGMAC 3.10a
Number of EMACs controllers supported 2 3 3 3
Reduced Media Independent Interface (RMII) for 10/100 No Yes Yes No
Gigabit Media Independent Interface (RGMII) Yes Yes Yes Yes
GMII adaptation to RMII Yes Yes Yes No
GMII adaptation to RGMII Yes Yes No Yes
GMII adaptation to SGMII Yes Yes Yes Yes
GMII adaptation to SGMII+ No No No Yes, Agilex™ 5 only. up to 2.5 Gbps

Enable TSN support

No

 No No Yes
Serial timestamp interface Yes Yes Yes Yes
ECC protection for internal memory Included Enhanced Enhanced Enhanced
ECC errors can be directly injected from the ECC controller N/A Yes Yes Yes
FIFO size

Rx: 4 KB

Tx: 4 KB

Rx: 16 KB

Tx: 4 KB

Rx: 16 KB

Tx: 16 KB

Rx: 16 KB

Tx: 32 KB
HPS PHY interface I/O bank location HPS I/O HPS shared I/O bank HPS dedicated I/O bank HPS dedicated I/O bank
HPS I/O PHY RGMII-ID support No Facilitated with delay elements in I/O element Enhanced support with delay elements in pin MUX22 Enhanced support with delay elements in pin MUX 22
22 Delay elements are more accurate than in the Arria 10 family. The skew range is larger and more consistent.
Level Two Title