Differences Among Altera® SoC Device Families

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ID 683648
Date 8/29/2025
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Differences Among Altera® SoC Device Families
Differences Among Altera® SoC Device Families x
Overview of HPS Modules HPS Micro Processor Unit Subsystem Differences Booting and Configuration Differences Cache Coherency Unit Differences Generic Interrupt Controller Differences HPS System Memory Management Unit Differences HPS On-Chip RAM Differences HPS Error Correction Differences HPS DMA Controller Differences HPS Clock Manager Differences HPS Reset Manager Differences HPS FPGA Manager Differences HPS System Manager Differences HPS Scan Manager Differences HPS Security Feature Differences HPS System Interconnect and Firewalls Differences HPS-FPGA Bridge Differences HPS General Purpose I/O Interface Differences I/O Pin Multiplexing Differences HPS Mailbox Differences HPS SDRAM Controller Subsystem Differences HPS NAND Flash Controller Differences HPS SD/eMMC Host Controller Differences Combo DLL PHY Differences HPS Quad SPI Flash Controller Differences HPS USB 2.0 OTG Controller Differences HPS USB 3.1 Gen1 Controller Differences HPS EMAC Differences HPS SPI Controller Differences HPS I2C Controller Differences I3C Controller Differences HPS UART Controller Differences HPS CAN Controller Differences HPS Timer Differences HPS Watchdog Timer Differences HPS CoreSight Debug and Trace Differences Revision History for Differences Among Altera® SoC Device Families
Differences Among Altera® SoC Device Families

Booting and Configuration Differences

Table 1.  FPGA Configuration Method Differences
FPGA Configuration Method Cyclone® V SoC,

Arria® V SoC

 Arria® 10 SoC Stratix® 10 SoC,

Agilex™ 7

F-Series/I-Series/

M-Series SoC

Agilex™ 5

E-Series/D-Series SoC,

Agilex™ 3

C-Series SoC
Active serial (AS) FPGA configuration block (CB) FPGA configuration subsystem (CSS) SDM SDM
Passive serial (PS) FPGA CB FPGA CSS N/A N/A
Fast passive parallel (FPP) FPGA CB, HPS FPGA Manager FPGA CSS, HPS FPGA Manager N/A N/A
Avalon® streaming interface (Avalon-ST) N/A N/A SDM SDM
Configuration via protocol (CvP) FPGA CB FPGA CSS SDM SDM
JTAG FPGA CB FPGA CSS SDM SDM
Supports early I/O release N/A Yes Yes Yes
Table 2.  Booting Differences
HPS Boot Feature Cyclone® V SoC,

Arria® V SoC

 Arria® 10 SoC Stratix® 10 SoC

Agilex™ 7

F-Series/I-Series/

M-Series SoC

Agilex™ 5

E-Series/D-Series SoC

Agilex™ 3

C-Series SoC
Initial HPS Image Loader HPS Boot ROM HPS Boot ROM SDM SDM SDM
HPS Boot from SD/eMMC Yes Yes Yes5 Yes 5 Yes5
HPS Boot from NAND Yes Yes Yes 5 Yes 5 Yes5
HPS Boot from Quad SPI (QSPI) Yes Yes Yes 5 Yes 5 Yes5
HPS Boot from CvP No No Yes Yes Yes
HPS Boot from Avalon® streaming interface (Avalon-ST) No No Yes 5 Yes 5 Yes 5
HPS Boot from FPGA Yes Yes No No 6 No6
HPS boots first, then HPS configures FPGA Yes Yes Yes Yes Yes
HPS Boot Image Compression No No Yes 5 Yes 5 Yes 5
HPS Boot Image Security No Yes Yes Yes Yes
Related Information
5 The initial HPS bootloader is loaded by the SDM, supporting the same features and image sources as for FPGA configuration.
6 Because the HPS bootloader is loaded by the SDM from the same source as the FPGA configuration image, the HPS does not have to boot from the FPGA image. This saves FPGA resources.
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