Differences Among Altera® SoC Device Families

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ID 683648
Date 8/29/2025
Public
Document Table of Contents
Document Table of Contents x
Differences Among Altera® SoC Device Families
Differences Among Altera® SoC Device Families x
Overview of HPS Modules HPS Micro Processor Unit Subsystem Differences Booting and Configuration Differences Cache Coherency Unit Differences Generic Interrupt Controller Differences HPS System Memory Management Unit Differences HPS On-Chip RAM Differences HPS Error Correction Differences HPS DMA Controller Differences HPS Clock Manager Differences HPS Reset Manager Differences HPS FPGA Manager Differences HPS System Manager Differences HPS Scan Manager Differences HPS Security Feature Differences HPS System Interconnect and Firewalls Differences HPS-FPGA Bridge Differences HPS General Purpose I/O Interface Differences I/O Pin Multiplexing Differences HPS Mailbox Differences HPS SDRAM Controller Subsystem Differences HPS NAND Flash Controller Differences HPS SD/eMMC Host Controller Differences Combo DLL PHY Differences HPS Quad SPI Flash Controller Differences HPS USB 2.0 OTG Controller Differences HPS USB 3.1 Gen1 Controller Differences HPS EMAC Differences HPS SPI Controller Differences HPS I2C Controller Differences I3C Controller Differences HPS UART Controller Differences HPS CAN Controller Differences HPS Timer Differences HPS Watchdog Timer Differences HPS CoreSight Debug and Trace Differences Revision History for Differences Among Altera® SoC Device Families
Differences Among Altera® SoC Device Families

Revision History for Differences Among Altera® SoC Device Families

Date Version Changes
August 2025 2025.08.29
  • Added information on the differences of Agilex™ 7 SoC, Agilex™ 5 SoC and Agilex™ 3 SoC in the following topics:
    • Overview of HPS Modules
    • HPS Micro Processor Unit Subsystem Differences
    • Booting and Configuration Differences
    • Cache Coherency Unit Differences
    • Generic Interrupt Controller Differences
    • HPS System Memory Management Unit Differences
    • HPS On-Chip RAM Differences
    • HPS Error Correction Differences
    • HPS DMA Controller Differences
    • HPS Clock Manager Differences
    • HPS Reset Manager Differences
    • HPS FPGA Manager Differences
    • HPS System Manager Differences
    • HPS Scan Manager Differences
    • HPS System Interconnect and Firewalls Differences
    • HPS-FPGA Bridge Differences
    • HPS General Purpose I/O Interface Differences
    • I/O Pin Multiplexing Differences
    • HPS Mailbox Differences
    • HPS SDRAM Controller Subsystem Differences
    • HPS NAND Flash Controller Differences
    • HPS SD/eMMC Host Controller Differences
    • Combo DLL PHY Differences
    • HPS Quad SPI Flash Controller Differences
    • HPS USB 2.0 OTG Controller Differences
    • USB 3.1 Gen1 Controller Differences
    • HPS EMAC Differences
    • HPS SPI Controller Differences
    • HPS I2C Controller Differences
    • I 3C Controller Differences
    • HPS UART Controller Differences
    • HPS CAN Controller Differences
    • HPS Timer Differences
    • HPS Watchdog Timer Differences
    • HPS CoreSight Debug and Trace Differences
  • Added Advanced Security Features Available in SDM-based Devices table.
  • Removed HPS Cache Coherency Controller Differences topic.
August 2018 2018.08.22 Corrections in Booting and Configuration Differences:
  • NAND configuration not supported by Stratix® 10 SoC
  • FPP configuration in Stratix® 10 SoC based on Avalon® -ST
April 2018 2018.04.11 Correction in "HPS SDRAM Controller Subsystem Differences": LPDDR3 not supported in the Intel® Stratix® 10 SoC
May 2017 2017.05.06 Additional detail about:
  • MPU ACP support
  • MPU cache error correction
  • Clock implementation
  • Stratix 10 security features
  • HPS-FPGA bridge latency support
  • Supported NAND flash memory widths
  • USB 2.0 OTG PHY connections
  • Corrected EMAC IP version number
  • EMAC FIFO sizes
  • EMAC I/O bank usage
  • EMAC RGMII-ID support
  • Details about SPI controller frame sizes, clocks, bit rates, and slave select
  • UART compatibility features
November 2016 2016.11.11
  • Added Stratix 10 SoC information
  • Reorganized for easier reference
  • Added IP version numbers for some third-party components
  • Added details about I/O configuration differences
  • Added booting and configuration differences

August 2014

2014.08.18

 Updated Arria 10 SoC information
January 2014 2014.01.15

Initial release.
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